• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 16 subscribers
  • Views 1049 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TS3A5018: I2S Interface

TS3A5018: how to reduce the cross-talk on TS3A5018

Oliver Ou
Intellectual 2845 points
Part Number: TS3A5018

Hi,

We connect TCAM_MDC to FPGA_MDC, and also have switch signal about both TCAM_MDC and JER_MCD pins.

and found larger cross-talk from FPGA_MDC to TCA_MDC. How to minimize the cross-talk? Do you have any suggestions.

here are schematic, layout and waveform for your reference.

Thanks.

  • 0
    TI__Mastermind 45340 points

    Oliver, 

    The ringing on the clock signal is significant on the undershoot.  The voltage is outside the recommended operating conditions of the TS3A5018 datasheet of 0V and even outside of the absolute maximum ratings of -0.5 V.  You will need reduce the ringing of the clock signal to be closer within the recommended operating conditions of the datasheet.   

    Common techniques to reduce clock ringing are to have proper termination where the source impedance matches the termination impedance, adding RC filter, reducing the slew rate of the clock signal, or reduce the trace length.    

    Thank you, 

    Adam