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TS5MP646: Recommended pattern when there is a constraint

K.Shidara
Expert 3225 points
Part Number: TS5MP646
Other Parts Discussed in Thread: TS5MP645,

Hi Team,

If you look at the layout example of the data sheet,

there is a pattern between the pins for the inner pins,

but is there a recommended layout when the pattern

can not pass between the pins?

Thanks

Best regards,

Shidara

  • 0
    TI__Mastermind 45340 points

    Shidara,

    There isn't any special layout pattern for the TS5MP645 device.  The recommendation is to use high speed layout best practices to ensure your PCB is not the limiting factor for your signal chain performance.  You would want to route your signals to be differentially paired as soon as possible for best impedance control, make sure the trace lengths are the same, avoid right angles, try not to use vias, etc.

    Thank you,

    Adam 

  • 0 in reply to Adam Torma
    TI__Expert 3225 points

    Hi Adam-san

    Thank you very much for the advice.

    One additional question, 

    Since there was a document of the evaluation board of the target IC,

    the contents were checked and the evaluation board was not a differential pair,

    and the pattern was drawn to TP as a single, but this is what purpose Is it designed?

    TMUX136 EVM User's guide

    Thanks

    Best regards,

    Shidara

  • 0 in reply to K.Shidara
    TI__Mastermind 45340 points

    Shidara,

    The evaluation module you referenced for the TS5MP646 purpose is for quick DC functional evaluation.  Differential routing is not needed for DC testing only for highspeed signaling performance.

    Thank you,

    Adam