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TMUX1104: Drain and Source Capacitance of FET based switches

Part Number: TMUX1104

Hi,

I am working on a design where I need to switch the incoming pulse in to two ways and the load resistance is quite high-around 1.5k Ohm to 5k Ohm.

Since the load impedance is high I assumed it might create some issues on the pulse shape due to BW limitation.

As I was going through the switch simulation tools section I couldn't find any TINA model or spice models. So I was thinking to simulate this with equivalent capacitance of source and drain w.r.t. GND and the load resistance in TINA. I have attached the TINA spice schematic here. My assumption is that the CSON and CDON capacitance mentioned in the datasheet is w.r.t. IC GND but it is not mentioned specifically that how these capacitance have been measured- Am I correct in this assumption? Usually for FETs capacitance are given in terms of CGD, CDS and CGS- but here I am not getting these data.

I can possibly reduce the load resistance and get my pulse shape as desired but the doubt still remains how these capacitance have been measured.

Thanks!

MandanOutput Signal gen.TSC

  • Mandan,

    The On-state capacitance in the datasheet is with respect to ground so you have the correct assumption for your simulation.  The value stated in the datasheet is including both the drain and the source capacitance so it would be better if you had 17.5 pF caps on the input and output.

    Thank you,

    Adam