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Part Number: TMUX1511
We are looking to use the TMUX1511 to isolate RMII signals between an Ethernet PHY and OMAP processor when the OMAP is not powered. In this state we are awaiting a WoL magic packet.
As the 50MHz clock is active (along with other signals) during this state, we require a means to isolate it so as not power the OMAP via the 3.3V domain.
I have tested the TMUX1511PWR on the bench, and when the switch is disabled by grounding the SEL pin, and with a 50MHz clock fed into either the S or D pins, there is a 50MHz clock at ~450mV pk-pk on the other pin.
We are using 3.3V to power the TMUX1511 and the 50MHz clock is DC 3.3V fed from a function generator (Tr = 3.0ns)
From the datatsheet the off isolation @ 50MHz should be -30dB, but we are not seeing anywhere near that level
Can you advise as to the issue?
Placing the control logic pins at ground logic low will create a high impedance path between S and D. This doesn't automatically mean that D will go to ground unless you have pull down resistors on the COM side of the circuit.
Can you post a Scope shot off the 50kHz signal on S and D?
Thank you and best regards,
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In reply to Ambroise Suter:
Yellow = Input on S1
Pink = Output on D1
SEL1 = 0V
In reply to Ian Davis20:
does the same happen when you hook up a logic low voltage to SEL? (between 0V and 0.45V)
And how is the off isolation on the other pins?
Yes there is no difference when SEL is between 0V and 0.45V.
The isolation between other pins is very good.
Adding a 3k3 pull down resistor on the output D reduced the output swing to around 120mV whilst using a sig gen as the input.
I tired this in-circuit with the actual 50MHz clock from the 10/100 Ethernet PHY going to the OMAP and the pull down resistor had no affect. More-over in this real setup the output voltage swing is ~450mV
Scope Trace: TMUX1511in off state in circuit inbetween PHY and OMAP
Pink = input into S
Yellow = output D
SEL = 0V
*Note different V/Div
Scope Trace: TMUX1511 in off state in circuit inbetween PHY and OMAP
Yellow = output D (with 1k pull down)
Just to be sure, did you try the 50MHz clock on other channels?
And could you share a partial schematic?
Yes, I have tried on all channels and get the same result.
We are at the stage of approving the IC before it makes it into our design, so I dont have a final schematic. I have however quickly drawn a schematic of how we would be using the IC. I have purposly left off siganls / components that are not relevant to this issue.
Is the Impedance on S & D known? the off isolation can be calculated as 10log10((Vout²/Rout) / (Vin²/Rin)) if the impedances are not the same.
Can you check with your set-up?
The input and output impedance should be matched between ~50-68 ohms.
As mentioned the schematic provided is roughly how we would like to use the switch. I am not trying to debug our circuit, I have been trying to prove on the bench that the switch behaves as per the datasheet before we include it in a further design, and I can't see how it does.
Are you able to supply a working test setup or better still provide scope traces of the switch isolating a 50MHz digital clock?
thank you for the details, I'll have to look into this in the lab, as we have not seen this behavior yet.
Thank you for your patience,
Hi Ian, we are expecting the results from the lab mid next week. I will post the results around Wednesday.
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