Part Number: TS3V340
When we set D(0V) connect to S1 and S2 is floating, we could measure a 0.3C~1V on S2 pin.
Could you help to explain why S2 is not 0V?
As shown in this App Note floating pins can have all sorts of implications. What is the VCC level and are all other signals disconnected? If not, what are their signal levels and frequencies?
Thank you and best regards,
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
In reply to Ambroise Suter:
D: LVDS signal.
S1: DC level = 0V with external DC cap blocking.
In reply to Patrick Chen(TPE System & Application):
depending on the frequency and voltage level the LVDS signal is running at, it could contribute up to 0.26V (500MHz, 3.3V) due to off-isolation (Figure 3 in the Datasheet).Other sources could come from parasitics within the CMOS switch.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.