• Resolved

SN74CBT3251: Vcc to Select & OE isolation?

Part Number: SN74CBT3251

Vcc will be 5V however the Select and OE pins will be driven by MCU at 3.3V. On the SN74CBT3251, are the Select & OE pins isolated from Vcc? Or do we need to ensure that the MCU has 5V tolerant pins?

Thank you

  • Cassidy,

    The SN74CBT3251 can have Vcc = 5V and the SEL and OE pins will work at 3.3 V since the Vih min voltage is 2 V.  Since the logic control pins are not at Vcc or ground you may some additional Icc current.

    More information on the extra current consumption can be seen in this application note Implications of slow or floating CMOS inputs.

    Thank you,


  • In reply to Adam Torma:

    Thank you Adam for the response!

    So based on the application note, the device has a pseudo/partial pull-up during a floating input because the P-channel transistor will be on if the Input is low. The device would then pull the input up until the N-channel transistor is on. However, the device would never be able to pull-up the input past vih because the P-channel transistor would then turn off and prevent further pull-up, correct? The main concern is the possibility of the device internally pulling up the input to Vcc and damaging the MCUs driving pin.

    The additional Icc you mentioned is the current from Vcc to GND due to a lower input voltage causing both transistors to be partially on (compared to a 5V level). This shouldn't affect/leak into the voltage of the input pin, correct?

    As long as we transition out of the 0.8V-2V range (3.3V logic high) we will have reduced Icc to the approximately the same amount as a 5V Logic level. Also, avoiding any floating circumstances should prevent unknown pull-up behavior. Is there any other possible circumstances that could cause the 5V Vcc to leak into the the input of the device or cause some sort of voltage transient on the input? And if so, would a simple weak pulldown or bushold circuit help prevent such Vcc to IO input leakage?
  • In reply to Cassidy Aarstad:


    1) The digital control logic is an input buffer so it will not drive any current out of the control logic pin and damage the MCU. 

    2)  Correct, the additional Icc is due to the input buffer on the control logic. 

    3) The extra current consumption will be ~1mA according to the app note for the SN74CBTXXXX family.  There will not be any issues with Vcc effecting the signal path since it is basically connected to the gate of the FET switch and has almost no leakage for the SN74CBTXXXX family. 


    Let me know if you have additional questions.

    Thank you,