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TS5A3166-Q1: About switch characterics and IBIS Model

user4822169
Prodigy 10 points
Part Number: TS5A3166-Q1
Other Parts Discussed in Thread: TS5A3166

Hello.

There are two question about TS5A3166-Q1

 1. Signal Transition

     I did the experiment of clock signal transition.

     I inputed clock signal at "COM" port [VIH 0.5V, VIL 0V, Frequency 20MHz, tR/tF 100ps (20%-80%)]

     I measure it at "NO" port.

     a. On state: OK

     b. Off state: I expected that no signal was measured, but there was signal transition during about 3ns (max level 0.3V).

    Question) Is this proper operation of this IC? I think that this is related to off isolation spec. Am i right?

                     And what is the input signal condition not to transit any(or very low level) signal?

 2. IBIS Model

   I got the IBIS Model on TI site and I opened it with Mentor company IBIS Model Editer (Viewer)

   I tried to check the switch On/Off characterics. But I couldn't opened "[Model]TS5A3166_B_18_S]"

   Please let me know how to see it.

   And confirm that this IBIS file is not operated on Power SI toool. 

Thanks.

  • 0
    TI__Mastermind 45340 points

    User4822169,

    1) These are solids state FET switches and do not have perfect isolation when they are off like a mechanical switch.  The paracitic leakage is stated in the leakage parameters.

    You can see that placing 4.5 V on the COM pin with the switch typically 4 nA of current will leak through the device. 

    However, you mention that there is only briefly a signal measured 3ns. Would you be able to show us the scope shot of the COM, NO and IN pin?  3ns seems to be within the turn off time and the glitch you maybe seeing could be due to the charge injection during the transition. 

    2) I have submitted this question to the modeling forum.  However Input/output Buffer Information Specification model is not valid on a passive FET switch signal path because the signal path is not buffered.

    Thank you,

    Adam