Please refer to the datasheet to get the timing specs for address change to signal output change. I have included a snippet from the datasheet on page 5. These specs call out the time for enable and disable from address or enable to output. Highlighted for max value across -40C to 125C.

Please let me know if this isn't what you are looking for.

The datasheet shows the Ten and Tdis for a given load capacitor and resistor. In the case of the CD74HC4051-Q1 datasheet those values are 1k resistor and both a 15pF and 50pF capacitor.

Lets look at examples where we vary the load resistor and capacitor:

If we have a given setup with a resistive and capacitive series connection we can calculate the time constant (tau) τ. Where τ = RC. Our first diagram shows a given resistor (5.6K) and a 1nF capacitor. The input voltage VG1 is a step response from 0 to 10V with a 10nS delayed response.

We can calculate the τ = (5.6K)*(1nF) = 5.6nS. This is shown in the output response where τ = 63.2% of the final value (6.32V)

We can see that the time constant is equal to 5.6nS (15nS - 10nS start delay).

If we increase the capacitive load by 20X then we should expect our τ to increase by 20X.

τ = (5.6K)*(20nF) = 112nS.

From the given waveform we can see the time constant behaves as expected.

Also remember that our time constant is not related to our input voltage. The time constant τ will remain the same for a given R and C value even if the input voltage went from 10V to 100V.

Additionally, if we add in a load resistor with the load capacitor we can predict the results. The load resistor can be used to calculate a thevinins equivalent resistance (Rth) assuming our capacitor is the load. To refresh on this topic please visit the explanation. This equivalent resistance can be used with the load capacitor to again calculate τ = (Rth)*(C).

For the sake of example we will use a load resistor equal to our series resistor such that our thevinins equivalent resistance is two resistors of equal value in parallel.

We can take our Rth = 2.8K with our C = 20nF. We can the calculate τ = (2.8K)*(20nF) = 56uS.

Again, the τ value is as we calcualted (66uS -10uS start delay = 56uS). The thing to note here is that our load resistance creates a voltage divider with our series resistance. In our case the two resistors are equal therefore our output voltage steady state value will be half of our input voltage (10V *0.5 =5V).

To summarize:

1) If we increase our load capacitor by a factor X. We can assume the time constant τ to increase by a factor of X if the resistance stays the same. τ = R*C

2) A larger load resistor will lead to a larger output voltage that can be calculated as a resistor divider. Vout =Vin * (Rload)/((Rload+Rseries)