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SN74LVC1G3157: SN74LVC1G3157 (1-channel 2:1) Output select bias voltage

Part Number: SN74LVC1G3157

Dear Sir,

I use 74LVC1G3157, may I know

When Vcc=5V,  A=3.3V , S=L,

- > B1=3.3V or 5V?


  • Steven,

    Placing a logic low on the S pin will cause the FETs on the B2 path to be Hi-Z and the FETs on the B1 path to have their gate voltages biased turning on the FET and allow conduction.   

    The SN74LVC1G3157 as you have shown above is a signal switch with "transmission gate architecture."  This transmission gate includes a NMOS FET in parallel with a PMOS FET.  This structure will allow the I/O pins (A and B1/B2) of the IC to pass "rail to rail" voltages meaning voltages from 0 to Vcc the supply rail for the IC.  If you set the Vcc pin to 5 V you will be able to pass any voltage from 0 to 5V on the I/O pins (A and B1/B2). 

    The on-state resistance of this switch is very low across the I/O voltages with supply voltage at 5V.  As you can see below and if you place 3.3 V on A pin there will be 3.3V on B1 pin since there is very little resistance across the signal path.

        You can find more information about signal switch operation in this application note.

    Thank you,