SN74CB3Q3305: Ioff with Vin = 5.5V

Joseph,

If Vcc = 0V, the voltage of the control pin should not effect the leakage spec on the I/O path, but I will need to place a device on my bench to confirm.

Why are you using the switch for that you need to have low leakage on the I/O path when Vcc = 0V?

Why did you choose the SN74CB3Q3305?

Thank you,
Adam

Adam,

Thanks for the prompt response!

I am using the switch to isolate signals from two power domains when either of the power domains are 0V.  I use one power domain (3.3V) for VCC, the signals connected to the I/O are 3.3V CMOS, and I use the other power domain (5V) to enable the switch through a 4.75k/10k voltage divider (the signals from the 5V domain are 3.3V CMOS).

Thus, when the 5V power domain is off (i.e. 0V) while the 3.3V domain is valid, the SN74CB3Q3305 OE input is pulled low (through the 10k resistor) and the switch is disabled.  When the 3.3V domain is 0V while the 5V domain is valid, I have the following situation:  Vcc = 0V, Vin = 3.75V (worst-case), Vi = 0 V and Vo = 0 to 3.6V.  Hence, my question.

My hope is the SN74CB3Q3305 will remain disabled in this situation and the Ioff spec is still applicable.  I also hope there is not a low impedance path to Vcc through the OE input (although since there is a 4.75k resistor between 5V and this input it should still be ok).

Although I am not certain you will be able to view it, I have inserted a jpeg image of the relevant circuitry below.

Regards,

Joe

Adam,

Have you had a chance to investigate this question any further?

Regards,

Joe

Joseph,

I don't see any issues with the schematic you have provided.  Are you seeing any leakage issues on your board in the case you described?

I have ordered samples and boards to test to see what happens to the leakage when Vcc=0V and there is a logic high voltage on the control logic pin.  I have not been able to get it on my bench yet to test but I do not predict to see any substantial leakage. 

When do you need this test completed?

Thank you,

Adam

Adam,

The board will be released for fabrication in ~2 weeks.  I intend to test for leakage when the boards are available, likely late July or early August.

I was hoping to verify the part will perform as needed prior to releasing the design.  If it does not perform as needed I would delay the release and change the design.

So if you had results (good or bad) prior to June 29 that would be great!  If that is not feasible, I will still release the design and take a chance that it will perform as needed.  And based upon your comments it does seem likely (but not guaranteed) that the switch will isolate the I/Os with Vcc=0V and a logic high on the control pin.

Again thanks so much for your support!

Regards,

Joe