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SN74CBTLV3126: Isolation Issue during the Power off condition

kiran habib
Prodigy 120 points
Part Number: SN74CBTLV3126
Other Parts Discussed in Thread: PCA9515A

Hi, 

For the Part SN74CBTLV3126 the datasheet specifies that the device supports  Partial-Power-Down-Mode (Ioff) and the device has isolation during power off.

Can you let me know what exactly it is meant by Partial-Power-Down-Mode and what conditions we need to maintain to achieve isolation during power off.

 We are seeing the device conducting from input(A's) to output(B's) when no supply(Vcc) is available with OE pin which is pulled down via by 10Kohm on our custom Board. When inputs(A's) are at 3.3V we are seeing a voltage level of 1.4V on outputs(B's). As such overall aim is have perfect isolation during power off state. Please let me know your thoughts on the same.

Regards,

Kiran

  • 0
    Guru 243980 points

    This is explained in section 4.6.20 of Understanding and Interpreting Standard-Logic Data Sheets (SZZA036); Ioff is

    the maximum leakage current into an input or output terminal of the device, with the specified voltage applied to the terminal and VCC = 0 V.

    What exactly does "no supply" mean? Please note that VCC must actually be at 0 V, not floating.

  • 0 in reply to Clemens Ladisch
    Prodigy 120 points
    Hi,

    Thanks for the information about Ioff. "No supply" essentially means Vcc=0V.

    The board with SN74CBTLV3126 part is plugged to an other board which is powered. OE pin is connected to common ground with 10k pull-down.But the input to this device is provided from the powered board.

    Kindly let us know how to achieve perfect isolation with this part and with Vcc=0V.


    Regards,
    Kiran
  • 0 in reply to kiran habib
    Guru 243980 points
    In theory, with VCC and OE both at 0 V, all I/Os should be high impedance.

    What exactly does that other board do with the 3126's power supply? Can you show the schematic?
  • 0 in reply to Clemens Ladisch
    Prodigy 120 points

    Hi,

    We don't have the schematic with switch buffer. we have wired it on the Main PCB and this is basically a testing for the revision change of the board.

    Note : OE's signals to buffer a not shown in above diagram but are pulled down by 10Kohm.

     

    The Host PCB provides 12V to main PCB after it is booted successfully. the signals connected to the buffer are from 3V3 powered domain. So the idea is to isolate a 3V3 powered signals from unpowered system till 12V from Host comes using a FET based buffer.

    But with above conditions we are seeing buffer not providing isolation.

    We also have I2C (Powered) signals coming from the Host PCB, using a PCA9515A from TI we have resolved the issue. we  also tried using same buffer (PCA9515A) for the UART an Interrupt (INTs) signals it worked fine with No supply condition. As such this buffer has Open drain IOs Which requires pull-ups to be present on the IOs but we can't connect pull-ups on (UART,INTs) signals as we don't have control to this signals.

    Also please suggest is there any other buffer to provide isolation with above conditions.

     

  • 0 in reply to kiran habib
    Guru 243980 points
    What regulator are you using? How does it force its output to 0 V when it has no input power? I guess it doesn't; try a pulldown resistor on the 3.3 V line.
  • 0 in reply to Clemens Ladisch
    Prodigy 120 points

    Hi,

    Thanks for the pull-down approach. below are testing observation.

    •  Pull-down of 168KOhm on 3V3 (Vcc) line, I am seeing a 0.2V on output (B's) of FET switch for the input(A's) of 3.3V.
    •  Pull-down of 100KOhm on 3V3 (Vcc) line same 0.2V output is present.
    •  Direct ground connection to Vcc pin of FET switch, same 0.2V on outputs.

    Please let me also know if there is any other IC that would work perfect for this scenario.

    Regards,

    Kiran

  • 0 in reply to Clemens Ladisch
    Prodigy 120 points

    Hi,

    Kindly give the response for the observation made with respect to buffer outputs. also please suggest the any other solution for the perfect isolation for above scenario.

  • 0 in reply to kiran habib
    TI__Mastermind 45350 points
    Kiran,

    The SN74CBTLV3126 is as solid state FET switch and does not have any buffering. Since it is a solid state device there will always be parasitic leakage currents that are characterized in the datasheet. For the Ioff spec of the SN74CBTLV3126 states that < 10uA of leakage current could pass through the device when Vcc = 0V.

    How are you measuring the undesired 200mV? If you are going into a high impedance node even 200nA of leakage into a 1M node can result in 200mV.

    What is your target for perfect isolation? Away to achieve perfect isolation is to use a mechanical switch that can have an airgap to achieve perfect isolation versus a high impedance semiconductor.

    Thank you,
    Adam