• Resolved

TIDA-00004: ALE of EthFw CPSW_9G drops all packets on TDA4

Prodigy 70 points

Replies: 10

Views: 73

Part Number: TIDA-00004

Hi TI Experts,

We are develop a VxWorks Virt MAC driver for TDA4 in order to perform network communication via CPSW9G (EthFw).

Now, we can attach to the EthFw through RPMSG and the EthFw can return:

  1. SessionId
  2. CoreKey
  3. RxMTU
  4. TxMTU
  5. Features
  6. AllocFlowIdx
  7. TxCPSWPsilDstId

After the attachment, we can successfully do “ping” or “DebugStatDump” on the EthFw.

 

But we are stuck in sending packet.

Our UDMA driver works. After sending a packet, we can get the Tx – finish interruption.

 

As per our investigation, these packets are all dropped by ALE.

Here are the traces. From “Port 0 Statistics”, we can see that all the packets have been counted in “aleDrop”.

From below trace, there is the ALE table. We compared ours with Linux’s. They are the same.

We also checked the Linux code. We didn’t find that Linux do any configuration for ALE. Maybe we missed something important.

 

Could you please give us some hints or clues? Then we can move on.

 

Thanks in advance!

 

Enabling clocks for CPSW_9G!

=======================================================

           CPSW Ethernet Firmware Demo            

=======================================================

CPSW_9G Test on MAIN NAVSS

IPC_echo_test (core : mcu2_0) .....

Remote device (core : mcu2_1) .....

CpswPhy_bindDriver: PHY 0: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK

Remote demo device (core : mcu2_0) .....

CpswPhy_bindDriver: PHY 3: OUI:080028 Model:23 Ver:01 <-> 'dp83867' : OK

PHY 0 is alive

PHY 3 is alive

PHY 12 is alive

PHY 15 is alive

PHY 23 is alive

Host MAC address: 70:ff:76:1d:87:64

[NIMU_NDK] CPSW has been started successfully

Cpsw_handleLinkUp: port 2: Link up: 1-Gpbs Full-Duplex

Function:app_ethrdev_srv_cb_attach_ext_handler,HostId:0,CpswType:1

Function:app_ethrdev_srv_cb_register_mac_handler,HostId:0,Handle:a2b371c0,CoreKey:38acb7e6, MacAddress:70:ff:76:1d:870

Cpsw_ioctlInternal: CPSW: Registered MAC address.ALE entry:10, Policer Entry:0Function:app_ethrdev_srv_cb_register_ip8

Failed to add Static ARP Entry

 

================LLI Table entries===========

 

Number of Static ARP Entries: 0

 

SNo.      IP Address         MAC Address 

------    -------------      ---------------

Function:app_ethrdev_srv_cb_client_notify_handler,HostId:0,Handle:38acb7e6,CoreKey:a2b371c0,NotifyId:RPMSG_KDRV_TP_ETn

 

     0: Vlanid: 012c, UTagged: 1ff, Mult: 1ff, UMult: 0, Member: 1ff RAW:[0 212c1ff1 ff0001ff]

     1: Vlanid: 0190, UTagged: 1ff, Mult: 1ff, UMult: 0, Member: 1ff RAW:[0 21901ff1 ff0001ff]

     2: Vlanid: 0191, UTagged: 1ff, Mult: 1ff, UMult: 0, Member: 1ff RAW:[0 21911ff1 ff0001ff]

     3: Vlanid: 0192, UTagged: 1ff, Mult: 1ff, UMult: 0, Member: 1ff RAW:[0 21921ff1 ff0001ff]

     4: Vlanid: 0193, UTagged: 1ff, Mult: 1ff, UMult: 0, Member: 1ff RAW:[0 21931ff1 ff0001ff]

     5: Vlanid: 0194, UTagged: 1ff, Mult: 1ff, UMult: 0, Member: 1ff RAW:[0 21941ff1 ff0001ff]

     6: Vlanid: 0195, UTagged: 1ff, Mult: 1ff, UMult: 0, Member: 1ff RAW:[0 21951ff1 ff0001ff]

     7: Vlanid: 0196, UTagged: 1ff, Mult: 1ff, UMult: 0, Member: 1ff RAW:[0 21961ff1 ff0001ff]

     8: Vlanid: 0197, UTagged: 1ff, Mult: 1ff, UMult: 0, Member: 1ff RAW:[0 21971ff1 ff0001ff]

     9: Address: 70ff761d8764, Port: 000 Se=1 Bl=0 TOUCH=0 AGE=0 TRUNK=0 RAW:[1 100070ff 761d8764]

    10: Address: 70ff761d8763, Port: 000 Se=0 Bl=0 TOUCH=0 AGE=0 TRUNK=0 RAW:[0 100070ff 761d8763]

 

1013 Free Entries

 

    0: POLICER_DST_MAC,ALE Index: 10

    0: POLICER_THREAD,THREAD ID:0

    0: POLICER_STATS: Hit: 0, RedHit: 0, YellowHit: 0

 

95 Free Entries

 

Port 0 Statistics

-----------------------------------------

  rxGoodFrames            = 6

  rxBcastFrames           = 1

  rxMcastFrames           = 5

  aleDrop                 = 6

  rxOctets                = 522

  txGoodFrames            = 2

  txBcastFrames           = 2

  txOctets                = 128

  octetsFrames64          = 3

  octetsFrames65to127     = 5

  netOctets               = 650

  portMaskDrop            = 6

  aleUnknownMcast         = 5

  aleUnknownMcastBcnt     = 458

  aleUnknownBcast         = 1

  aleUnknownBcastBcnt     = 64

  txPri[2]                = 2

  txPriBcnt[2]            = 128

 

 

External Port 0 Statistics

-----------------------------------------

 

 

External Port 1 Statistics

-----------------------------------------

 

 

External Port 2 Statistics

-----------------------------------------

  rxGoodFrames            = 17

  rxBcastFrames           = 2

  rxMcastFrames           = 15

  aleDrop                 = 15

  rxOctets                = 1673

  octetsFrames64          = 4

  octetsFrames65to127     = 10

  octetsFrames128to255    = 3

  netOctets               = 1673

  portMaskDrop            = 15

  aleUnknownMcast         = 5

  aleUnknownMcastBcnt     = 455

  aleUnknownBcast         = 1

  aleUnknownBcastBcnt     = 64

 

 

External Port 3 Statistics

-----------------------------------------

 

 

External Port 4 Statistics

-----------------------------------------

 

 

External Port 5 Statistics

-----------------------------------------

 

 

External Port 6 Statistics

-----------------------------------------

 

 

External Port 7 Statistics

-----------------------------------------

 

  • Hi GuishanQin,

    Thank you for posting to E2E! Please allow us to reassign this thread.; it has been assigned to the Isolation forum due to TIDA-00004 ownership, which differs from TDA4.


    Respectfully,
    Manuel Chavez

  • In reply to Manuel Chavez:

    Hello GuishanQin,

    Thanks for the very detailed post and great to see you following all the correct debug steps pinpointing the exact location where issue is. 

    To help you with ale port mask drop issue, can you please let me know the SDK version you are using?

    Also, do you have access to CCS? If yes, can you share the output of the "print ALE table" GEL function? Note - the debug GELs for CPSW are located in PDK component under the directory pdk\packages\ti\drv\cpsw\tools\debug_gels

    There are other gel files as well here which will help you print statistics etc.

    Regards,

    Prasad Jondhale
    Jacinto, TI India

  • In reply to Prasad Jondhale:

    Hi Prasad,

    I appreciate your kindly help! I'm Yabing, Guishan's colleagure. We are working together on this job.

    Our SDK version: ti-processor-sdk-linux-automotive-j7-evm-06_01_01_02

    We didn't compile the psdk but simply made a SD card from the Linux SDK via command: 

    sudo ./mksdboot.sh --device /dev/sdc --sdk ..
     
    Since we are using the pre-built images, including Linux's and EthFw's, we only know the Linux version is 06_01_01_02 but are not sure the EthFw's.
    Could you please let us know what "CCS" is? I'm sorry that we are not very familiar with TI's building, configuration and debug environment.
    On our hand, we have a psdk: psdk_rtos_auto_j7_06_02_00_21.
    According to your guidance, I find some ".gel" files under "psdk_rtos_auto_j7_06_02_00_21/pdk/packages/ti/drv/cpsw/tools/debug_gels".
    But I don't know how to use them on the TDA4. Should we rebuild the psdk? or there are some ways in which we can run commands via the serial port of the EthFw?
    By the way, is psdk_rtos_auto_j7_06_02_00_21 compatible with ti-processor-sdk-linux-automotive-j7-evm-06_01_01_02?
    A lot of questions:) Thanks for your help and patience!:)
  • In reply to Prasad Jondhale:

    Hi  Prasad

    Below is the output of the ALE gel. Seem the same as R5 firmware output. 

    Could you help to check what is wrong ? Thanks.

    MAIN_Cortex_R5_0_0: GEL Output: -------CPSW9G ALE TABLE----------------------
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: Entry 0 - VLAN INNER
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE = 2
    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID = 300
    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG = 0
    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD = 511
    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR = 0
    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST = 511
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: Entry 1 - VLAN INNER
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE = 2
    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID = 400
    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG = 0
    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD = 511
    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR = 0
    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST = 511
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: Entry 2 - VLAN INNER
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE = 2
    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID = 401
    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG = 0
    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD = 511
    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR = 0
    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST = 511
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: Entry 3 - VLAN INNER
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE = 2
    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID = 402
    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG = 0
    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD = 511
    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR = 0
    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST = 511
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: Entry 4 - VLAN INNER
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE = 2
    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID = 403
    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG = 0
    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD = 511
    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR = 0
    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST = 511
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: Entry 5 - VLAN INNER
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE = 2
    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID = 404
    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG = 0
    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD = 511
    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR = 0
    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST = 511
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: Entry 6 - VLAN INNER
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE = 2
    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID = 405
    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG = 0
    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD = 511
    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR = 0
    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST = 511
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: Entry 7 - VLAN INNER
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE = 2
    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID = 406
    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG = 0
    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD = 511
    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR = 0
    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST = 511
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: Entry 8 - VLAN INNER
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE = 2
    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID = 407
    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG = 0
    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD = 511
    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240
    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR = 0
    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0
    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST = 511
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: Entry 9 - Unicast
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: TRUNK = 0
    MAIN_Cortex_R5_0_0: GEL Output: PORT_NUMBER = 0
    MAIN_Cortex_R5_0_0: GEL Output: BLOCK = 0
    MAIN_Cortex_R5_0_0: GEL Output: SECURE = 1
    MAIN_Cortex_R5_0_0: GEL Output: TOUCH = 0
    MAIN_Cortex_R5_0_0: GEL Output: AGEABLE = 0
    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE = 1
    MAIN_Cortex_R5_0_0: GEL Output: UNICAST_ADDR = 0x000070FF 0x761D8764
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: Entry 10 - Unicast
    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------
    MAIN_Cortex_R5_0_0: GEL Output: TRUNK = 0
    MAIN_Cortex_R5_0_0: GEL Output: PORT_NUMBER = 0
    MAIN_Cortex_R5_0_0: GEL Output: BLOCK = 0
    MAIN_Cortex_R5_0_0: GEL Output: SECURE = 0
    MAIN_Cortex_R5_0_0: GEL Output: TOUCH = 0
    MAIN_Cortex_R5_0_0: GEL Output: AGEABLE = 0
    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE = 1
    MAIN_Cortex_R5_0_0: GEL Output: UNICAST_ADDR = 0x000070FF 0x761D8763
    MAIN_Cortex_R5_0_0: GEL Output: Completed analysis of 1024 ALE entries

  • In reply to GuishanQin:

    Hello Guishan,

    Glad you are able to use CCS and use the debug gels.

    Before going into debug, can you please let me know if you can use "psdk_rtos_auto_j7_06_02_00_21"?

    EthFw in this version of the release has some bug fixes which may be root cause of your issue.

    From the ALE dump, I believe issue can be because of

    1. Add ALE entry to receive broadcast packets

    Add below function in ethfw\apps\app_remoteswitchcfg_client\mcu_2_1\main_tirtos.cand call it in IpAddrHookFxn

    +int32_t CpswApp_setAleMulticastEntry(uint8_t macAddr[CPSW_MAC_ADDR_LEN],
    + uint32_t vlanId,
    + uint32_t numIgnBits,
    + uint32_t portMask)
    +{
    + int32_t status;
    + Cpsw_Handle hCpsw = Cpsw_getHandle(gCpswMainAppObj.cpswType);
    + Cpsw_IoctlPrms prms;
    + CpswAle_AddEntryOutArgs setMcastOutArgs;
    + CpswAle_SetMcastEntryInArgs setMcastInArgs;
    +
    + memcpy(&setMcastInArgs.addr.addr[0], macAddr,
    + sizeof(setMcastInArgs.addr.addr));
    + setMcastInArgs.addr.vlanId = vlanId;
    +
    + setMcastInArgs.info.superFlag = false;
    + setMcastInArgs.info.fwdState = CPSW_ALE_FWDSTLVL_FORWARDING;
    + setMcastInArgs.info.portMask = portMask;
    + setMcastInArgs.info.numIgnBits = numIgnBits;
    +
    + CPSW_IOCTL_SET_INOUT_ARGS(&prms, &setMcastInArgs, &setMcastOutArgs);
    +
    + status = Cpsw_ioctl(hCpsw, CpswAppSoc_getCoreId(), CPSW_ALE_IOCTL_ADD_MULTICAST,
    + &prms);
    + if (status != CPSW_SOK)
    + {
    + CpswAppUtils_print("CpswApp_setAleMulticastEntry() failed CPSW_ALE_IOCTL_ADD_MULTICAST: %d\n",
    + status);
    + }

    + return status;

    +}
    +

    Calling syntax

    +    uint8_t bCastAddr[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};

    + /* Add ALE entry for broadcast mac address. Note this is needed as the broadcast

    + * is disabled via unknownRegMcastFloodMask and other flags in ALE init config.
    + * In EthFw we need broadcast to handle ARP entries for clients
    + */
    + CpswApp_setAleMulticastEntry(&bCastAddr[0U],
    + 0U, /* vlanId */
    + 0U, /* numIgnBits */
    + CPSW_ALE_ALL_PORTS_MASK);

    2. "secure" bit not set for the remote client entry.

    MAIN_Cortex_R5_0_0: GEL Output: TRUNK = 0

    MAIN_Cortex_R5_0_0: GEL Output: PORT_NUMBER = 0
    MAIN_Cortex_R5_0_0: GEL Output: BLOCK = 0
    MAIN_Cortex_R5_0_0: GEL Output: SECURE = 0
    MAIN_Cortex_R5_0_0: GEL Output: TOUCH = 0
    MAIN_Cortex_R5_0_0: GEL Output: AGEABLE = 0
    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE = 1
    MAIN_Cortex_R5_0_0: GEL Output: UNICAST_ADDR = 0x000070FF 0x761D8763

    Can you please check if function CpswRemoteApp_addHostPortEntry has secure bit set to true?

    Regards,

    Prasad Jondhale
    Jacinto, TI India

  • In reply to Prasad Jondhale:

    Hi Prasad,

    Thanks for your great help!

    As you suggested, we are using "psdk_rtos_auto_j7_06_02_00_21" now.

    After I updated "ethfw\apps\app_remoteswitchcfg_client\mcu_2_1\main_tirtos.c", I met some build errors. I added below code to resolve them.

    #include <ti/drv/cpsw/examples/cpsw_apputils/inc/cpsw_mcm.h>
    typedef struct
    {
        /* Core Id */
        uint32_t coreId;
    
        /* CPSW instance type */
        Cpsw_Type cpswType;
    
        /* Multiclient manager handles */
        CpswMcm_CmdIf mcmCmdIf[CPSW_COUNT];
    
        /* UDMA driver handle */
        Udma_DrvHandle hUdmaDrv;
    
        /* Use default rx flow */
        bool useDefaultRxFlow;
    } CpswMain_AppObj;
    
    
    static CpswMain_AppObj gCpswMainAppObj =
    {
    #if defined(SOC_AM65XX)
        .cpswType         = CPSW_2G,
    #elif defined(SOC_J721E)
        .cpswType         = CPSW_9G,
    #endif
        .useDefaultRxFlow = true,
    };

    Hope that I didn't do anything wrong.

    With your fix, the situation is better! ALE doesn't drop every packet anymore.

    Port 0 Statistics

    -----------------------------------------

      rxGoodFrames            = 32

      rxBcastFrames           = 32

      aleDrop                 = 17

      rxOctets                = 9998

      octetsFrames64          = 17

      octetsFrames512to1023   = 15

      netOctets               = 9998

      portMaskDrop            = 17

     

     

    External Port 0 Statistics

    -----------------------------------------

     

     

    External Port 1 Statistics

    -----------------------------------------

     

     

    External Port 2 Statistics

    -----------------------------------------

      txGoodFrames            = 15

      txBcastFrames           = 15

      txOctets                = 8910

      octetsFrames512to1023   = 15

      netOctets               = 8910

      txPri[1]                = 15

      txPriBcnt[1]            = 8910

    But after analysis, we found that all the packets which can pass through ALE were DHCP packets from CPSW9 FW.

    The packets from VxWorks were still all dropped.

    We tried to check the issue of "SECURE=0", but we can't find a function named "CpswRemoteApp_addHostPortEntry". We only can find

    CpswProxy_addHostPortEntry for client and CpswAppUtils_addHostPortEntry for server and both of them do:
    setUcastInArgs.info.secure  = true;
     
    We performed  "print ALE table" GEL function when we run Linux on A72. It showed that Linux's "SECURE" was also 0.
    Could you please help us to know what magic Linux does, which makes the switch relay its packets?
    Thanks in advance!
  • In reply to Yabing Liu:

    Hello Yabing,

    If you are using psdk_rtos_auto_j7_06_02_00_21, fixes are part of the application already. You don't need to modify anything.

    You had shared earlier ALE table logs from CCS, I believe it was for SDK6.1.

    Can you please share ALE table for SDK6.2? Share without any modification in default code and with modification.

    Regards,

    Prasad Jondhale
    Jacinto, TI India

  • In reply to Prasad Jondhale:

    Hi Prasad,

    Thanks for your quick reply!

    Yes, I'm using "psdk_rtos_auto_j7_06_02_00_21". My SD card was created from "ti-processor-sdk-linux-automotive-j7-evm-06_02_00".

    In order to guarantee that the EthFw's version is 06_02_00_21, I built EthFw from the source code and replaced j7-main-r5f0_0-fw with app_remoteswitchcfg_server.xer5f and j7-main-r5f0_1-fw with app_remoteswitchcfg_client.xer5f in the SD card.

    As you requested, I dump ALE table twice: one is based on the default code, the other is with the fix which you provided above.

    It seems that there is no difference between them.

    ALE Table with default code

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: -------CPSW9G ALE TABLE----------------------

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 0 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 300

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 1 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 400

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 2 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 401

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 3 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 402

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 4 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 403

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 5 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 404

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 6 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 405

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 7 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 406

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 8 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 407

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 9 - Unicast

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: TRUNK            = 0

    MAIN_Cortex_R5_0_0: GEL Output: PORT_NUMBER      = 0

    MAIN_Cortex_R5_0_0: GEL Output: BLOCK            = 0

    MAIN_Cortex_R5_0_0: GEL Output: SECURE           = 1

    MAIN_Cortex_R5_0_0: GEL Output: TOUCH            = 0

    MAIN_Cortex_R5_0_0: GEL Output: AGEABLE          = 0

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE       = 1

    MAIN_Cortex_R5_0_0: GEL Output: UNICAST_ADDR     = 0x000070FF 0x761D8764

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 10 - Unicast

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: TRUNK            = 0

    MAIN_Cortex_R5_0_0: GEL Output: PORT_NUMBER      = 0

    MAIN_Cortex_R5_0_0: GEL Output: BLOCK            = 0

    MAIN_Cortex_R5_0_0: GEL Output: SECURE           = 0

    MAIN_Cortex_R5_0_0: GEL Output: TOUCH            = 0

    MAIN_Cortex_R5_0_0: GEL Output: AGEABLE          = 0

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE       = 1

    MAIN_Cortex_R5_0_0: GEL Output: UNICAST_ADDR     = 0x000070FF 0x761D8763

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 11 - Multicast

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: PORT_MASK        = 0x000001FF

    MAIN_Cortex_R5_0_0: GEL Output: SUPER            = 0

    MAIN_Cortex_R5_0_0: GEL Output: MCAST IGNORE BITS= 0

    MAIN_Cortex_R5_0_0: GEL Output: MCAST_FWD_STATE  = 0

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE       = 1

    MAIN_Cortex_R5_0_0: GEL Output: MULTICAST_ADDR   = 0x0000FFFF 0xFFFFFFFF

    MAIN_Cortex_R5_0_0: GEL Output: Completed analysis of 1024 ALE entries

    ALE Table with fix

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: -------CPSW9G ALE TABLE----------------------

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 0 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 300

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 1 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 400

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 2 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 401

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 3 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 402

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 4 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 403

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 5 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 404

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 6 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 405

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 7 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 406

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 8 - VLAN INNER

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE        = 2

    MAIN_Cortex_R5_0_0: GEL Output: IVLAN_ID           = 407

    MAIN_Cortex_R5_0_0: GEL Output: NO FRAG           = 0

    MAIN_Cortex_R5_0_0: GEL Output: REG_MCAST_FLOOD   = 511

    MAIN_Cortex_R5_0_0: GEL Output: VLAN FWD Untagged Egress = 240

    MAIN_Cortex_R5_0_0: GEL Output: LMT NEXT HDR      = 0

    MAIN_Cortex_R5_0_0: GEL Output: UNREG_MCAST_FLOOD = 0

    MAIN_Cortex_R5_0_0: GEL Output: VLAN_MEMBER_LIST  = 511

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 9 - Unicast

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: TRUNK            = 0

    MAIN_Cortex_R5_0_0: GEL Output: PORT_NUMBER      = 0

    MAIN_Cortex_R5_0_0: GEL Output: BLOCK            = 0

    MAIN_Cortex_R5_0_0: GEL Output: SECURE           = 1

    MAIN_Cortex_R5_0_0: GEL Output: TOUCH            = 0

    MAIN_Cortex_R5_0_0: GEL Output: AGEABLE          = 0

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE       = 1

    MAIN_Cortex_R5_0_0: GEL Output: UNICAST_ADDR     = 0x000070FF 0x761D8764

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 10 - Unicast

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: TRUNK            = 0

    MAIN_Cortex_R5_0_0: GEL Output: PORT_NUMBER      = 0

    MAIN_Cortex_R5_0_0: GEL Output: BLOCK            = 0

    MAIN_Cortex_R5_0_0: GEL Output: SECURE           = 0

    MAIN_Cortex_R5_0_0: GEL Output: TOUCH            = 0

    MAIN_Cortex_R5_0_0: GEL Output: AGEABLE          = 0

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE       = 1

    MAIN_Cortex_R5_0_0: GEL Output: UNICAST_ADDR     = 0x000070FF 0x761D8763

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output:  Entry 11 - Multicast

    MAIN_Cortex_R5_0_0: GEL Output: ---------------------------------------------

    MAIN_Cortex_R5_0_0: GEL Output: PORT_MASK        = 0x000001FF

    MAIN_Cortex_R5_0_0: GEL Output: SUPER            = 0

    MAIN_Cortex_R5_0_0: GEL Output: MCAST IGNORE BITS= 0

    MAIN_Cortex_R5_0_0: GEL Output: MCAST_FWD_STATE  = 0

    MAIN_Cortex_R5_0_0: GEL Output: ENTRY_TYPE       = 1

    MAIN_Cortex_R5_0_0: GEL Output: MULTICAST_ADDR   = 0x0000FFFF 0xFFFFFFFF

  • In reply to Yabing Liu:

    Hello Yabing,

    I believe your issue might be because of known issue in EthFw - ADASVISION-3866 [EthFw] ARP requests are not serviced for the remote clients

    http://downloads.ti.com/jacinto7/esd/processor-sdk-rtos-jacinto7/latest/exports/docs/ethfw/ethfw_release_notes.html#Known_Issues

    To confirm it, can you please try below?

    1. Ping from VxWorks Virt MAC driver terminal to PC IP address. This should work.

    2. Now ping from PC to virt-mac.

    VxWorks Virt MAC driver

    Regards,

    Prasad Jondhale
    Jacinto, TI India

  • In reply to Prasad Jondhale:

    Hello Prasad

    Great thanks for your help those days.

    Our issue goes away after comparing Ti's linux code carefully and changes some UDMA/VIRT_MAC related logic.

    I will follow the ARP issues you mentioned.

    So I'd like to close this ticket as resolved.