CC2538: SSI TX fifo: how it works?

Hi,

in a project we have cc2538 that is slave on SPI bus and it have to receive command from SPI master chip.

I design a protocol based on two operation: write operation is for communication master-to-slave, while read is for slave-to-master operation (means slave as some output for master).

The protocol works in this way:

1. the master initiate the communication clearing CS line, sending 2byte with operation code and 1byte with length
2. slave react:
   1. if is a write operation 4th to len-th byte will be received from slave and do what have to do.
   2. if is a read operation 4th to len-th  byte is from slave to master
3. master end the communication rising the CS line

I 'm testing the protocol and implementation simulating the master with another cc2538, but this is just for develope purpose. I choose to catch CS line with an GPIO interrupt to be able to do something to prepare and terminate the operation. I configure SSI with Motorola frame format, SPO=0 SPH=1, 8 bit word. the baud rate is 1Mhz.

My implementation with write operation works fine, I have some problem in read operations.

I wasn't able to answer correctly from slave to master, on cc2538 I do:

1. GPIO interrupt catch CS line falling edge and enable SPI
2. on SSI ISR receive and elaborate comunication header:
   1. move bytes from RxFifo to a local buffer if 3  bytes are in buffer:
      1. if is a read operation and txfifo is not full: copy from a position in RAM n-byte in TxFifo
      2. if is a write operation wait all bytes is tranfered
3. master clock for n bytes:
   1. if is a read operation master transmit n null byte (0x00) slave should transfer what I put in TxFifo
   2. if is a write operation master transmit n byte of payload
4. GPIO interrupt catch CS line rising edge, disable SPI and prepare for new operation

The problem is at point 3a: the slave doesn't send the bytes I put in fifo.

Looks the Txfifo was write only when chip select is not active. The result I have is: first time it send all 0x00, second time the answer of first operation, third time the answer of second.