In my design, the CC1101 receives fine if RSSI is better than -65dBm, but looses nearly all packets if signal strength is just slightly lower. At -65dBm I receive over 90% of all sent packets, at -70dBm I am at roughly 1%. RSSI is value read from appended status bytes.
Configuration and Receive Function is given below:
0x07, // IOCFG2 0x2E, // IOCFG1 0x2E, // IOCFG0 0x47, // FIFOTHR 0xD3, // SYNC1 0x91, // SYNC0 0x07, // PKTLEN 0x0C, // PKTCTRL1 0x44, // PKTCTRL0 0x00, // ADDR 0x00, // CHANNR 0x06, // FSCTRL1 0x00, // FSCTRL0 0x21, // FREQ2 0x65, // FREQ1 0x6A, // FREQ0 0xCA, // MDMCFG4 0x83, // MDMCFG3 0x16, // MDMCFG2 0x22, // MDMCFG1 0xF8, // MDMCFG0 0x34, // DEVIATN 0x07, // MCSM2 0x3E, // MCSM1 0x38, // MCSM0 0x16, // FOCCFG 0x6C, // BSCFG 0x43, // AGCCTRL2 0x58, // AGCCTRL1 0x91, // AGCCTRL0 0x0D, // WOREVT1 0x8A, // WOREVT0 0x38, // WORCTRL 0x56, // FREND1 0x10, // FREND0 0xE9, // FSCAL3 0x2A, // FSCAL2 0x00, // FSCAL1 0x1F, // FSCAL0
// this function is called upon pin interrupt from GDO2 (configured to interrupt at packet received with correct crc
void ITec_HandleRX() {
CC1101_ReadRxFifo((7 + 2)); // 7 byte packet length + 2 byte CRC and rssi
xITecBufferEntry_t *pxTmp = (xITecBufferEntry_t *)(g_xSpi.acRxBuf + 1); // spi receive buffer
if (((pxTmp->cLinkQuality & CC1101_CRCOK_MASK) == CC1101_CRCOK_MASK) &&
(CalcChecksum(&pxTmp->xPacket) == pxTmp->xPacket.cCB)) {
RBuf_Write(&g_xITec_RX_Queue, pxTmp);
}
}
I looked at the interrupt line with an oscilloscope, and there really are very few spikes (received packet interrupts). To me it seems that receiving already fails in the CC1101 Chip.
If Schematic snippet or other information is needed, I'll be happy to provide what I can.
