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CC3120: Synchronization of command and response between MCU and CC3120 through SPI interface

Part Number: CC3120

Hi,

    We are developing the host driver of CC3120, and the MCU communicates with the CC3120 through the SPI interface.

    According to the data sheet, host should pull down the nHIB pin and then high to reset the CC3120. After receiving the IRQ from CC3120, host should send the 4-byte sync pattern and then read back the response. By tracing the source code in the SDK, host driver issues SPI read operation right after sending out the 4-byte sync pattern. Without any synchronization mechanism between host and CC3120, how could we make sure that CC3120's response is ready when host driver sends out the SPI read command?

    By the way, the data sheet says that the maximum SPI clock for CC3120 is 20MHz. What is the minimum SPI clock that could make CC3120 work correctly?

    Thanks.

       Todd

  • I think this question should be focused on receiving the reset IRQ from CC3120. The MCU will send the 4-byte sync pattern and then read the response. Other command and response exchange should be synchronized by the CC_IRQ.

    Thanks.

    Todd
  • Hi Todd,

    The host will keep reading the CNYS word (see the code that follows the "NWP_IF_READ_CHECK(g_pCB->FD, &pBuf[0], 8);" ) until he gets the expected value (or until the timeout expires).
    If you still suspect issues, you can add a delay between the write and the read. 80usec delay should make sure the NWP is ready with response.

    The minimum SPI clock limit might be impacted by the command watchdog timeout (time to wait for a response).
    What is the clock speed that you are considering?

    Br,
    Kobi
  • Hi Kobi,

    I think you are right, the code will keep reading the sync words until timeout. I set the SPI clock rate to 10MHz, and it works.

    Thanks for your help.

    Todd