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CC2541 OAD: Image A CRC fails

Other Parts Discussed in Thread: CC2541

Hi, 

I'm experience a strange and annoying issue with CC2541.

My Images are asymmetric and Image A is larger than Image B.

Updating Image B from Image A works but updating Image A from B doesn't; the Image is correct ( jtag read back) but the CRC verification fails.

The CRC verification fails also if I append Image A ((jtag) when Image B is already flashed but it passes when only bootloader and Image A are present.

It's quite strange and also a big problem for us, can anyone help debugging it?

Thanks

Paolo

Here's my xcl configuration for Image A

////////////////////////////////////////////////////////////////////////////////
//
// Segment limits
//

//
// XDATA available to the program.
//
-D_XDATA_BEG=0x0000
-D_XDATA_END=0x1EFF

//
// The 8052 IDATA is overlayed on the SoC XDATA space from 0x1F00-0x1FFF.
//
-D_IDATA_BEG=0x0A  // Must reserve 0x08-0x09 for the IBM INTVEC re-direct.
-D_IDATA_END=0xFF

//
// CODE
//
-D_CODE_BEG=0x0830             // First page is for the IBM which intercepts the H/W INTVECS.
-D_CODE_END=0x4FFF             // Next 7 pages of Bank 0.
//
-D_BANK4_BEG=0x48800           // Last 10 pages of Bank 4.
-D_BANK4_END=0x4FFFF
//
-D_BANK5_BEG=0x58000
-D_BANK5_END=0x5FFFF
//
-D_BANK6_BEG=0x68000
-D_BANK6_END=0x6FFFF
//
-D_BANK7_BEG=0x78000
// Cannot use the lock-bits page in a boot-loadable image; skip NV pages area.
-D_BANK7_END=0x7E7FF

//
// Register bank setup
//
-D?REGISTER_BANK=0             // Default register bank (0,1,2,3).
-D_REGISTER_BANK_BEG=0         // Start address for default register bank (00,08,10,18).

//
// PDATA page setup
//
-D?PBANK_NUMBER=00             // High byte of 16-bit address to the PDATA area.

//
// Virtual register setup
//

-D_BREG_BEG=0x00               // The bit address where the BREG segments starts.
                               // Must be placed on: _BREG_BEG%8=0 where _BREG_BEG <= 0x78.

-D?VB=0x20                     // ?VB is used when referencing BREG as whole byte.
                               // Must be placed on: ?VB=0x20+_BREG_BEG/8.

////////////////////////////////////////////////////////////////////////////////
//
// IDATA memory
//

// Setup "bit" segments (only for '__no_init bool' variables).
-Z(BIT)BREG=_BREG_BEG
-Z(BIT)BIT_N=0-7F

-Z(DATA)REGISTERS+8=_REGISTER_BANK_BEG
-Z(DATA)BDATA_Z,BDATA_N,BDATA_I=20-2F
-Z(DATA)VREG+_NR_OF_VIRTUAL_REGISTERS=_IDATA_BEG-7F
-Z(DATA)PSP,XSP=_IDATA_BEG-7F
-Z(DATA)DOVERLAY=_IDATA_BEG-7F
-Z(DATA)DATA_I,DATA_Z,DATA_N=_IDATA_BEG-7F

-U(IDATA)0-7F=(DATA)0-7F
-Z(IDATA)IDATA_I,IDATA_Z,IDATA_N=_IDATA_BEG-_IDATA_END
-Z(IDATA)ISTACK+_IDATA_STACK_SIZE#_IDATA_BEG-_IDATA_END
-Z(IDATA)IOVERLAY=_IDATA_BEG-FF

////////////////////////////////////////////////////////////////////////////////
//
// ROM memory
//

-Z(CODE)CHECKSUM=0x0800-0x0801
-Z(CODE)IMAGE_HEADER=0x802-0x80F
-Z(CODE)AES_HEADER=0x810-0x82F

-Z(CODE)INTVEC=_CODE_BEG-_CODE_END
-Z(CODE)BIT_ID,BDATA_ID,DATA_ID,IDATA_ID,IXDATA_ID,PDATA_ID,XDATA_ID=_CODE_BEG-_CODE_END
-Z(CODE)CSTART,RCODE,DIFUNCT,NEAR_CODE=_CODE_BEG-_CODE_END
-Z(CODE)BANK_RELAYS=_CODE_BEG-_CODE_END

-D_SLEEP_CODE_SPACE_START=(_CODE_END-7)
-D_SLEEP_CODE_SPACE_END=(_CODE_END)
-Z(CODE)SLEEP_CODE=_SLEEP_CODE_SPACE_START-_SLEEP_CODE_SPACE_END

//
// Setup for constants located in code memory:
//
-Z(CODE)CODE_C=_CODE_BEG-_CODE_END
//
// Define segments for const data in flash.
// First the segment with addresses as used by the program (flash mapped as upper XDATA)
-P(CONST)XDATA_ROM_C=0x8000-0xFFFF
//
// Then the segment with addresses as put in the hex file (flash bank 5).
-P(CODE)XDATA_ROM_C_FLASH=_BANK5_BEG-_BANK5_END
//
// Finally link these segments (XDATA_ROM_C_FLASH is the initializer segment for XDATA_ROM_C,
// we map the flash in the XDATA address range instead of copying the data to RAM)
-QXDATA_ROM_C=XDATA_ROM_C_FLASH

-Z(CODE)ALIGNED_CODE|2=_CODE_BEG-_CODE_END,_BANK4_BEG-_BANK4_END,_BANK5_BEG-_BANK5_END,\
_BANK6_BEG-_BANK6_END,_BANK7_BEG-_BANK7_END
-P(CODE)BANKED_CODE=_CODE_BEG-_CODE_END,_BANK4_BEG-_BANK4_END,_BANK5_BEG-_BANK5_END,\
_BANK6_BEG-_BANK6_END,_BANK7_BEG-_BANK7_END

////////////////////////////////////////////////////////////////////////////////
//
// XDATA memory
//

-Z(XDATA)XSTACK+_XDATA_STACK_SIZE=_XDATA_BEG-_XDATA_END
-Z(XDATA)XDATA_Z,XDATA_I,PDATA_Z=_XDATA_BEG-_XDATA_END
-P(XDATA)XDATA_N=_XDATA_BEG-_XDATA_END

-cx51

////////////////////////////////////////////////////////////////////////////////
//
// Misc.
//

//
// Offset fix for the unconventional bank numbering for this SOC (root bank is callled "bank 0").
-D_FIRST_BANK_ADDR=0x10000

//
// NOTE: The -M option below is needed when linker output should be in "intel-extended" (HEX)
//       file format for banked code model. It translates the logical addresses for the EW8051
//       to physical addresses in the output file format. Without this, the HEX output file will
//       include 32 kB blocks of zero bytes/gap in between each code bank.
//
-M(CODE)[(_CODEBANK_START+_FIRST_BANK_ADDR)-(_CODEBANK_END+_FIRST_BANK_ADDR)]*_NR_OF_BANKS+0x10000=\
0x8000

// When -M is used to build debug output, XLINK gives warning [w69] which is safely ignored.
-ww69=i

// When INTVEC is relocated, XLINK gives error [e18] which is safely ignored.
-we18=i

//
// Fill code gaps with 0xFFFF for monolithic binary file with no addressing.
//
-HFFFF

//
// Skip CRC & SHDW when calculating the CRC.
//
-J2,crc=8005,=0804-_BANK7_END

//
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

Here's my xcl configuration for Image B

////////////////////////////////////////////////////////////////////////////////
//
// Segment limits
//

//
// XDATA available to the program.
//
-D_XDATA_BEG=0x0000
-D_XDATA_END=0x1EFF

//
// The 8052 IDATA is overlayed on the SoC XDATA space from 0x1F00-0x1FFF.
//
-D_IDATA_BEG=0x0A // Must reserve 0x08-0x09 for the IBM INTVEC re-direct.
-D_IDATA_END=0xFF

//
// CODE
//
-D_CODE_BEG=0x5030 // Last 7 pages of Bank 0.
-D_CODE_END=0x7FFF
//
-D_BANK1_BEG=0x18000
-D_BANK1_END=0x1FFFF
//
-D_BANK2_BEG=0x28000
-D_BANK2_END=0x2FFFF
//
-D_BANK3_BEG=0x38000
-D_BANK3_END=0x3FFFF
//
-D_BANK4_BEG=0x48000
-D_BANK4_END=0x487FF // First 6 pages of Bank 4.

//
// Register bank setup
//
-D?REGISTER_BANK=0 // Default register bank (0,1,2,3).
-D_REGISTER_BANK_BEG=0 // Start address for default register bank (00,08,10,18).

//
// PDATA page setup
//
-D?PBANK_NUMBER=00 // High byte of 16-bit address to the PDATA area.

//
// Virtual register setup
//

-D_BREG_BEG=0x00 // The bit address where the BREG segments starts.
// Must be placed on: _BREG_BEG%8=0 where _BREG_BEG <= 0x78.

-D?VB=0x20 // ?VB is used when referencing BREG as whole byte.
// Must be placed on: ?VB=0x20+_BREG_BEG/8.

////////////////////////////////////////////////////////////////////////////////
//
// IDATA memory
//

// Setup "bit" segments (only for '__no_init bool' variables).
-Z(BIT)BREG=_BREG_BEG
-Z(BIT)BIT_N=0-7F

-Z(DATA)REGISTERS+8=_REGISTER_BANK_BEG
-Z(DATA)BDATA_Z,BDATA_N,BDATA_I=20-2F
-Z(DATA)VREG+_NR_OF_VIRTUAL_REGISTERS=_IDATA_BEG-7F
-Z(DATA)PSP,XSP=_IDATA_BEG-7F
-Z(DATA)DOVERLAY=_IDATA_BEG-7F
-Z(DATA)DATA_I,DATA_Z,DATA_N=_IDATA_BEG-7F

-U(IDATA)0-7F=(DATA)0-7F
-Z(IDATA)IDATA_I,IDATA_Z,IDATA_N=_IDATA_BEG-_IDATA_END
-Z(IDATA)ISTACK+_IDATA_STACK_SIZE#_IDATA_BEG-_IDATA_END
-Z(IDATA)IOVERLAY=_IDATA_BEG-FF

////////////////////////////////////////////////////////////////////////////////
//
// ROM memory
//

-Z(CODE)CHECKSUM=0x5000-0x5001
-Z(CODE)IMAGE_HEADER=0x5002-0x500F
-Z(CODE)AES_HEADER=0x5010-0x502F

-Z(CODE)INTVEC=_CODE_BEG-_CODE_END
-Z(CODE)BIT_ID,BDATA_ID,DATA_ID,IDATA_ID,IXDATA_ID,PDATA_ID,XDATA_ID=_CODE_BEG-_CODE_END
-Z(CODE)CSTART,RCODE,DIFUNCT,NEAR_CODE=_CODE_BEG-_CODE_END
-Z(CODE)BANK_RELAYS=_CODE_BEG-_CODE_END

-D_SLEEP_CODE_SPACE_START=(_CODE_END-7)
-D_SLEEP_CODE_SPACE_END=(_CODE_END)
-Z(CODE)SLEEP_CODE=_SLEEP_CODE_SPACE_START-_SLEEP_CODE_SPACE_END

//
// Setup for constants located in code memory:
//
-Z(CODE)CODE_C=_CODE_BEG-_CODE_END
//
// Define segments for const data in flash.
// First the segment with addresses as used by the program (flash mapped as upper XDATA)
-P(CONST)XDATA_ROM_C=0x8000-0xFFFF
//
// Then the segment with addresses as put in the hex file (flash bank 4).
-P(CODE)XDATA_ROM_C_FLASH=_BANK4_BEG-_BANK4_END
//
// Finally link these segments (XDATA_ROM_C_FLASH is the initializer segment for XDATA_ROM_C,
// we map the flash in the XDATA address range instead of copying the data to RAM)
-QXDATA_ROM_C=XDATA_ROM_C_FLASH

-Z(CODE)ALIGNED_CODE|2=_CODE_BEG-_CODE_END,_BANK1_BEG-_BANK1_END,_BANK2_BEG-_BANK2_END,\
_BANK3_BEG-_BANK3_END,_BANK4_BEG-_BANK4_END
-P(CODE)BANKED_CODE=_CODE_BEG-_CODE_END,_BANK1_BEG-_BANK1_END,_BANK2_BEG-_BANK2_END,\
_BANK3_BEG-_BANK3_END,_BANK4_BEG-_BANK4_END

////////////////////////////////////////////////////////////////////////////////
//
// XDATA memory
//

-Z(XDATA)XSTACK+_XDATA_STACK_SIZE=_XDATA_BEG-_XDATA_END
-Z(XDATA)XDATA_Z,XDATA_I,PDATA_Z=_XDATA_BEG-_XDATA_END
-P(XDATA)XDATA_N=_XDATA_BEG-_XDATA_END

-cx51

////////////////////////////////////////////////////////////////////////////////
//
// Misc.
//

//
// Offset fix for the unconventional bank numbering for this SOC (root bank is callled "bank 0").
-D_FIRST_BANK_ADDR=0x10000

//
// NOTE: The -M option below is needed when linker output should be in "intel-extended" (HEX)
// file format for banked code model. It translates the logical addresses for the EW8051
// to physical addresses in the output file format. Without this, the HEX output file will
// include 32 kB blocks of zero bytes/gap in between each code bank.
//
-M(CODE)[(_CODEBANK_START+_FIRST_BANK_ADDR)-(_CODEBANK_END+_FIRST_BANK_ADDR)]*_NR_OF_BANKS+0x10000=\
0x8000

// When -M is used to build debug output, XLINK gives warning [w69] which is safely ignored.
-ww69=i

// When INTVEC is relocated, XLINK gives error [e18] which is safely ignored.
-we18=i

//
// Fill code gaps with 0xFFFF for monolithic binary file with no addressing.
//
-HFFFF

//
// Skip CRC & SHDW when calculating the CRC.
// -J2,crc=8005,= D_CODE_BEG of cc254x_f256_imgB.xc + 4 -_BANK4_END
-J2,crc=8005,=5004-_BANK4_END

//
////////////////////////////////////////////////////////////////////////////////

BIM Main.c defines:

#define BIM_IMG_A_PAGE 1
#define BIM_IMG_A_AREA 69

#define BIM_IMG_B_PAGE 10
#define BIM_IMG_B_AREA (124 - BIM_IMG_A_AREA)

#define BIM_CRC_OSET 0x00
#define BIM_HDR_OSET 0x00

  • Hello Paolo,

    I would recommend using CC Debugger to step through the BIM to verify the CRC is being computed on the right ranges of flash. Also, you can read out the flash to confirm it's being programmed as expected. This should be a good starting point.

    Best wishes
  • Hi JXS,

    That is exactly what I was doing and my settings are all correct.

    The issue is in TI code provided with the bootloader that is creating un-initilized bit that are configured randomly in the dma controller, ( DMAExecCrc() function)

      // One whole page (or len) at a time
      HAL_DMA_SET_VLEN( dmaCh0_p, HAL_DMA_VLEN_USE_LEN );         /* Using the length field */
      HAL_DMA_SET_LEN(dmaCh0_p, len);

    I think TI should be much more careful when distributing this code that resides is un-modifiable firmware section and costed me one and half day of debugging.

  • In case is not clear

    HAL_DMA_SET_LEN(dmaCh0_p, len);

    is the missing initialization.
  • Hi Paolo,

    What version of BLE Stack were you using when you encountered this problem?

    I looked through the BIM code in my version of the TI BLE Stack and I DO see this initialization "HAL_DMA_SET_LEN(dmaCh0_p, len);".  However, I DO NOT see the following piece of code, "HAL_DMA_SET_VLEN( dmaCh0_p, HAL_DMA_VLEN_USE_LEN );", as you mention in an earlier post.  BTW, I am using BLE Stack 1.4.0.

    I was hoping that you could clarify this for me.

    Thanks in advance

    Regards,
    KK