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Hi,
I need to implement the software algorithm to support programming of TI processors CC1310 and CC2640 via the JTAG port.
For doing this, I need to access to TI Technical Specs I can't find on your web site.
The document should describe: "CC1310 and CC2640 programming via JTAG port".
Can anybody help?
Thanks.
Michael
Take a look at this thread:
Regards,
Michel
Hi Michael,
Have you looked at the CC26xx TRM? More specifically, take a look at chapter 5 section 5.2 and 5.2.1
If that still doesn't answer your questions, I suggest that you click "Reject answer" on my previous post to have other people look at your request. It will help TI employees know which questions were answered, and which not.
Michel
We have carefully studied the SWCU117F Technical Reference Manual, especially the chapter 5 section 5.2 and 5.2.1.
On those sections are described JTAG commands, but none of them is for the Flash programming.
There must be another document (it's not public, perhaps it's under NDA), with JTAG commands for PROGRAMMING THE MICRO-CONTROLLERS' FLASH VIA JTAG PORT.
I'd like to clarify that the company I represent, Lynxar Technologies, is a professional ISP tool provider.
We do not just need to CC1310 and CC2640 for our own purposes, we need to implement programming algorithms on our ISP Platform that will be used by OEMs/EMSs ( they are Texas Instrument customers! ).
Those OEMs/EMSs (Texas Instrument customer) are in need to program CC1310 and CC2640, the production is quite massive and they need to use our DeviceClip tool to perform Flash programming operations. The need 16 devices to be programmed at once. Our tool allows this. But we need to support the microcontroller VIA JTAG PORT.
To sum up:
On SWCU117F Technical Reference Manual, some JTAG commands are mentioned, but none is dedicated to Flash Programming (Debug port).
Unresolved questions:
1) Which are the registers used for Flash Programming (write enable, busy, etc.)?
2) Does the Flash access take place through a TAP?
3) If so, which one?
4) Otherwise, is Cortex M3 DAP involved? Which address? Which bus width (32-/64-bit)?
As you can see, SWCU117F Technical Reference Manual do not mention any of the above questions.
I'd to thank in advance anybody that can help us. My customer (a TI customer) is waiting for this.
Michael
Lynxar Technologies
www.lynxartech.com
Hello TIBAO,
And thanks for the message you sent me yesterday.
We already had this information. It is not very clear.
Notes regarding your message:
Is this the only information available to program CC1310 and CC2640 flash programming via JTAG port?
If so, a very small micro-kernel has to be developed (and then it shall be run in RAM). What software development tool do you suggest us to use? The standard TI software development tool includes RTOS, which makes to output code too bed to be run in RAM, and it would also be inefficient.
Do you have some source code examples to simplify the our development job?
From the documentation we've so far received, we realised that the following steps has to be accomplished:
1) We are to develop an application through CCxx development environment. This application should execute Flash programming through ROM API and some synchronization "mailboxes"
2) We should then stop the ARM.
3) Load the micro-kernel on CCxx on a RAM zone
4) Load blocks of code to be flashed to a different RAM zone.
5) Execute the micro-kernel and wait for its completato by "polling" mailboxes.
6) Repeat operations from 4) until the whole flash is written.
Con you confirm that the steps above are correct?
It's almost a year we are trying to discover how to support CCxx processors by JTAG. We sold some other tools by implementing other non-JTAG communication interfaces. Now we have a customer that absolutely need JTAG interface.
Can we count on you (and your suggestions) to finally implement support CCxx processors by JTAG?
It would be great if we could communicate directly. May I have (privately) your mail address and/or Phone number?
Thank you very much. I owe you.
Regards,
Michael
AllanD,
CC13xx programming is done on-chip. This means that Programming the CC13xx through JTAG requires that you implement the cJTAG/JTAG protocol on your external MCU, For programming, you need to load a flashloader image into RAM (that calls driverlib functions for erase/program), in addition to the data you want to program.
In your use-case, may I suggest the integrated CC13xx bootloader?
Then you can reset the CC13xx into boot by connecting the external MCU to the CC13xx reset pin + a trigger pin to enter the bootloader. Then you can use the command interface to program the device. More info on the bootloader here. swra466
TIABO
Hi,
with the TI-RTOS kernel you will never be able to shrink a TI-RTOS application down to RAM size. The only 3 options I see for you are:
I think that variant 1 is enough for your purpose. I don't know why TI does not publish the source code of their loader though, but you may use the source code of the serial ROM bootloader as an inspiration. I suggest to bring that into a working state in flash first, then link it to RAM and then try to implement the JTAG mailbox.
The following links might be helpful for you:
Hi Richard W.
Thank you for your quick reply and the link to the serial ROM boot loader!
I am going to be looking at this today and at first look at the serial ROM boot loader source code as a base. This appears to be a good place to start.
I agree, a release of the source code for the JTAG loader would be useful and would speed up this development.
I would like to make a suggestion to release the JTAG loader source, even under NDA would be acceptable but take time to go through the NDA process.
AllanD
Allan,
For your non-RTOS code, make sure you power up the GPIO module and the power domain.
Something like this:
// Power on periperal domain
PRCMPowerDomainOn(PRCM_DOMAIN_PERIPH);
while(PRCMPowerDomainStatus(PRCM_DOMAIN_PERIPH) != PRCM_DOMAIN_POWER_ON);
// Power on the GPIO peripheral
PRCMPeripheralRunEnable(PRCM_PERIPH_GPIO);
PRCMLoadSet();
while ( !PRCMLoadGet() );
Hi Richard W.
I seem to be making progress with this.
I am now attempting to locate the program to run in RAM.
I have created a simple LED blinking application using a timer with interrupt to verify I can do this.
When I attempt to relocate to RAM it appears to function correctly, but I receive no interrupts.
I am going to copy some relevant files, and hope these give insight to what is going on.
I have been digging around and some how I don't think the interrupt vector table is relocated to SRAM as I expected.
This is a combination of resources that I could find online and what was in the above "source code of the serial ROM bootloader" link.
Basically I created a new empty CCS project, copied the compiler and linker scripts from the bootloader project, altered them for the CC1350, and added the timer logic.
Looking at a dump result of a build I have the following, it is a little long, sorry...
If there is a better way to post code it would be appreciated to know.
This is a part of the original cc13x0f128.cmd file:
/* Retain interrupt vector table variable */
--retain=g_pfnVectors
/* Override default entry point. */
--entry_point ResetISR
/* Allow main() to take args */
--args 0x8
/* Suppress warnings and errors: */
/* - 10063: Warning about entry point not being _c_int00 */
/* - 16011, 16012: 8-byte alignment errors. Observed when linking in object */
/* files compiled using Keil (ARM compiler) */
--diag_suppress=10063,16011,16012
/* The following command line options are set as part of the CCS project. */
/* If you are building using the command line, or for some reason want to */
/* define them here, you can uncomment and modify these lines as needed. */
/* If you are using CCS for building, it is probably better to make any such */
/* modifications in your CCS project and leave this file alone. */
/* */
/* --heap_size=0 */
/* --stack_size=256 */
/* --library=rtsv7M3_T_le_eabi.lib */
/* The starting address of the application. Normally the interrupt vectors */
/* must be located at the beginning of the application. */
#define FLASH_BASE 0x0
#define FLASH_SIZE 0x20000
#define RAM_BASE 0x20000000
#define RAM_SIZE 0x5000
#define GPRAM_BASE 0x11000000
#define GPRAM_SIZE 0x2000
/* System memory map */
MEMORY
{
/* Application stored in and executes from internal flash */
FLASH (RX) : origin = FLASH_BASE, length = FLASH_SIZE
/* Application uses internal RAM for data */
SRAM (RWX) : origin = RAM_BASE, length = RAM_SIZE
/* Application can use GPRAM region as RAM if cache is disabled in the CCFG
(DEFAULT_CCFG_SIZE_AND_DIS_FLAGS.SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM = 0) */
GPRAM (RWX): origin = GPRAM_BASE, length = GPRAM_SIZE
}
/* Section allocation in memory */
SECTIONS
{
.intvecs : > FLASH_BASE
.text : > FLASH
.const : > FLASH
.constdata : > FLASH
.rodata : > FLASH
.binit : > FLASH
.cinit : > FLASH
.pinit : > FLASH
.init_array : > FLASH
.emb_text : > FLASH
.ccfg : > FLASH (HIGH)
.vtable : > SRAM
.vtable_ram : > SRAM
vtable_ram : > SRAM
.data : > SRAM
.bss : > SRAM
.sysmem : > SRAM
.stack : > SRAM (HIGH)
.nonretenvar : > SRAM
.TI.noinit : > SRAM
.gpram : > GPRAM
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
/* Hide section from older compilers not supporting the "ramfunc" attribute.
See processors.wiki.ti.com/.../Placing_functions_in_RAM */
.TI.ramfunc : {} load=FLASH, run=SRAM, table(BINIT)
#endif
#endif
}
/* Create global constant that points to top of stack */
/* CCS: Change stack size under Project Properties */
__STACK_TOP = __stack + __STACK_SIZE;
This is what I did to alter it to use sram:
/* Retain interrupt vector table variable */
--retain=g_pfnVectors
/* Override default entry point. */
--entry_point ResetISR
/* Allow main() to take args */
--args 0x8
/* Suppress warnings and errors: */
/* - 10063: Warning about entry point not being _c_int00 */
/* - 16011, 16012: 8-byte alignment errors. Observed when linking in object */
/* files compiled using Keil (ARM compiler) */
--diag_suppress=10063,16011,16012
/* The following command line options are set as part of the CCS project. */
/* If you are building using the command line, or for some reason want to */
/* define them here, you can uncomment and modify these lines as needed. */
/* If you are using CCS for building, it is probably better to make any such */
/* modifications in your CCS project and leave this file alone. */
/* */
/* --heap_size=0 */
/* --stack_size=256 */
/* --library=rtsv7M3_T_le_eabi.lib */
/* The starting address of the application. Normally the interrupt vectors */
/* must be located at the beginning of the application. */
#define FLASH_BASE 0x0
#define FLASH_SIZE 0x20000
#define RAM_BASE 0x20000000
#define RAM_SIZE 0x5000
#define GPRAM_BASE 0x11000000
#define GPRAM_SIZE 0x2000
/* System memory map */
MEMORY
{
/* Application stored in and executes from internal flash */
FLASH (RX) : origin = FLASH_BASE, length = FLASH_SIZE
/* Application uses internal RAM for data */
SRAM (RWX) : origin = RAM_BASE, length = RAM_SIZE
/* Application can use GPRAM region as RAM if cache is disabled in the CCFG
(DEFAULT_CCFG_SIZE_AND_DIS_FLAGS.SET_CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM = 0) */
GPRAM (RWX): origin = GPRAM_BASE, length = GPRAM_SIZE
}
/* Section allocation in memory */
SECTIONS
{
.intvecs : > RAM_BASE
.text : > SRAM
.const : > SRAM
.constdata : > SRAM
.rodata : > SRAM
.binit : > SRAM
.cinit : > SRAM
.pinit : > SRAM
.init_array : > SRAM
.emb_text : > SRAM
.ccfg : > FLASH (HIGH)
.vtable : > SRAM
.vtable_ram : > SRAM
vtable_ram : > SRAM
.data : > SRAM
.bss : > SRAM
.sysmem : > SRAM
.stack : > SRAM (HIGH)
.nonretenvar : > SRAM
.TI.noinit : > SRAM
.gpram : > GPRAM
#ifdef __TI_COMPILER_VERSION__
#if __TI_COMPILER_VERSION__ >= 15009000
/* Hide section from older compilers not supporting the "ramfunc" attribute.
See processors.wiki.ti.com/.../Placing_functions_in_RAM */
.TI.ramfunc : {} load=SRAM, run=SRAM, table(BINIT)
#endif
#endif
}
/* Create global constant that points to top of stack */
/* CCS: Change stack size under Project Properties */
__STACK_TOP = __stack + __STACK_SIZE;
Here is the resulting .map file showing how things are now arranged...
****************************************************************************** TI ARM Linker Unix v16.9.1 ****************************************************************************** >> Linked Thu Jun 29 18:38:57 2017 OUTPUT FILE NAME: <CC1350_boot.out> ENTRY POINT SYMBOL: "ResetISR" address: 20000f89 MEMORY CONFIGURATION name origin length used unused attr fill ---------------------- -------- --------- -------- -------- ---- -------- FLASH 00000000 00020000 00000060 0001ffa0 R X GPRAM 11000000 00002000 00000000 00002000 RW X SRAM 20000000 00005000 00001210 00003df0 RW X SEGMENT ALLOCATION MAP run origin load origin length init length attrs members ---------- ----------- ---------- ----------- ----- ------- 00000000 00000000 00000008 00000008 rw- 00000000 00000000 00000008 00000008 rw- .args 0001ffa8 0001ffa8 00000058 00000058 r-- 0001ffa8 0001ffa8 00000058 00000058 r-- .ccfg 20000000 20000000 00000ff8 00000ff8 r-x 20000000 20000000 000000c8 000000c8 r-- .intvecs 200000c8 200000c8 00000f30 00000f30 r-x .text 20001000 20001000 000000e0 00000000 rw- 20001000 20001000 000000c8 00000000 rw- .vtable_ram 200010c8 200010c8 00000018 00000000 rw- .data 200010e0 200010e0 00000038 00000038 r-- 200010e0 200010e0 00000038 00000038 r-- .cinit 20004f00 20004f00 00000100 00000000 rw- 20004f00 20004f00 00000100 00000000 rw- .stack SECTION ALLOCATION MAP output attributes/ section page origin length input sections -------- ---- ---------- ---------- ---------------- .intvecs 0 20000000 000000c8 20000000 000000c8 startup_ccs.obj (.intvecs) .text 0 200000c8 00000f30 200000c8 00000130 driverlib.lib : setup.obj (.text:NOROM_SetupAfterColdResetWakeupFromShutDownCfg3) 200001f8 000000ec : setup.obj (.text:NOROM_SetupAfterColdResetWakeupFromShutDownCfg2) 200002e4 000000cc : setup.obj (.text:TrimAfterColdResetWakeupFromShutDown) 200003b0 000000a4 : setup.obj (.text:NOROM_SetupTrimDevice) 20000454 000000a0 : setup.obj (.text:NOROM_SetupAfterColdResetWakeupFromShutDownCfg1) 200004f4 000000a0 main.obj (.text:timer_setup) 20000594 0000009c rtsv7M3_T_le_eabi.lib : memcpy_t2.obj (.text) 20000630 0000007a : memset_t2.obj (.text) 200006aa 00000002 startup_ccs.obj (.text:FaultISR) 200006ac 00000070 driverlib.lib : chipinfo.obj (.text:NOROM_ChipInfo_GetHwRevision) 2000071c 00000070 : setup.obj (.text:NOROM_SetupSetVddrLevel) 2000078c 00000070 rtsv7M3_T_le_eabi.lib : autoinit.obj (.text) 200007fc 0000006c driverlib.lib : setup.obj (.text:NOROM_SetupGetTrimForAmpcompCtrl) 20000868 00000068 : setup.obj (.text:NOROM_SetupGetTrimForAnabypassValue1) 200008d0 00000068 rtsv7M3_T_le_eabi.lib : copy_decompress_lzss.obj (.text:decompress:lzss) 20000938 00000060 driverlib.lib : osc.obj (.text:NOROM_OSCClockSourceSet) 20000998 0000005c main.obj (.text:led_setup) 200009f4 00000054 rtsv7M3_T_le_eabi.lib : exit.obj (.text) 20000a48 00000050 driverlib.lib : setup.obj (.text:NOROM_SetupSetCacheModeAccordingToCcfgSetting) 20000a98 0000004c rtsv7M3_T_le_eabi.lib : cpy_tbl.obj (.text) 20000ae4 00000048 driverlib.lib : chipinfo.obj (.text:NOROM_ChipInfo_GetChipFamily) 20000b2c 00000040 : timer.obj (.text:NOROM_TimerIntRegister) 20000b6c 00000040 rtsv7M3_T_le_eabi.lib : boot.obj (.text) 20000bac 00000034 driverlib.lib : interrupt.obj (.text:NOROM_IntRegister) 20000be0 00000030 : setup.obj (.text:NOROM_SetupSetAonRtcSubSecInc) 20000c10 00000030 : timer.obj (.text:TimerIntNumberGet) 20000c40 0000002c : ddi.obj (.text:NOROM_DDI32RegWrite) 20000c6c 0000002c : osc.obj (.text:NOROM_OSCClockSourceGet) 20000c98 0000002c : setup.obj (.text:NOROM_SetupGetTrimForRadcExtCfg) 20000cc4 0000002a main.obj (.text:TimerEventControl) 20000cee 0000002a main.obj (.text:TimerLoadSet) 20000d18 0000002a main.obj (.text:TimerPrescaleSet) 20000d42 00000002 startup_ccs.obj (.text:IntDefaultHandler) 20000d44 00000020 driverlib.lib : setup.obj (.text:NOROM_SetupGetTrimForXoscHfCtl) 20000d64 0000001e main.obj (.text:TimerEnable) 20000d82 00000002 startup_ccs.obj (.text:NmiSR) 20000d84 0000001c main.obj (.text:GPIO_setOutputEnableDio) 20000da0 0000001c main.obj (.text:ISR_TimerInterrupt_Handler) 20000dbc 0000001c driverlib.lib : setup.obj (.text:NOROM_SetupGetTrimForAmpcompTh2) 20000dd8 0000001c : setup.obj (.text:NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim) 20000df4 0000001c main.obj (.text:PRCMLoadGet) 20000e10 00000018 main.obj (.text:GPIO_clearDio) 20000e28 00000018 main.obj (.text:GPIO_setDio) 20000e40 00000018 main.obj (.text:GPIO_toggleDio) 20000e58 00000018 driverlib.lib : setup.obj (.text:NOROM_SetupGetTrimForAdcShModeEn) 20000e70 00000018 : setup.obj (.text:NOROM_SetupGetTrimForAdcShVbufEn) 20000e88 00000018 : setup.obj (.text:NOROM_SetupGetTrimForAmpcompTh1) 20000ea0 00000018 : setup.obj (.text:NOROM_SetupGetTrimForDblrLoopFilterResetVoltage) 20000eb8 00000018 : setup.obj (.text:NOROM_SetupGetTrimForRcOscLfIBiasTrim) 20000ed0 00000018 : setup.obj (.text:NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio) 20000ee8 00000018 main.obj (.text:TimerIntEnable) 20000f00 00000018 rtsv7M3_T_le_eabi.lib : args_main.obj (.text) 20000f18 00000016 driverlib.lib : chipinfo.obj (.text:NOROM_ThisCodeIsBuiltForCC13xxHwRev20AndLater_HaltIfViolated) 20000f2e 00000002 rtsv7M3_T_le_eabi.lib : mpu_init.obj (.text) 20000f30 00000014 : _lock.obj (.text) 20000f44 00000012 main.obj (.text:TimerIntClear) 20000f56 00000010 main.obj (.text:IntMasterEnable) 20000f66 00000002 rtsv7M3_T_le_eabi.lib : startup.obj (.text) 20000f68 00000010 driverlib.lib : setup.obj (.text:NOROM_SetupGetTrimForXoscHfFastStart) 20000f78 00000010 : setup.obj (.text:NOROM_SetupGetTrimForXoscHfIbiastherm) 20000f88 00000010 startup_ccs.obj (.text:ResetISR) 20000f98 00000010 main.obj (.text:main) 20000fa8 0000000e driverlib.lib : setup.obj (.text:NOROM_SetupSignExtendVddrTrimValue) 20000fb6 0000000e rtsv7M3_T_le_eabi.lib : copy_decompress_none.obj (.text:decompress:none) 20000fc4 0000000c driverlib.lib : cpu.obj (.text:NOROM_CPUcpsid) 20000fd0 0000000c : cpu.obj (.text:NOROM_CPUcpsie) 20000fdc 0000000c main.obj (.text:PRCMLoadSet) 20000fe8 0000000c rtsv7M3_T_le_eabi.lib : copy_zero_init.obj (.text:decompress:ZI) 20000ff4 00000004 : pre_init.obj (.text) .binit 0 20000000 00000000 .cinit 0 200010e0 00000038 200010e0 00000013 (.cinit..data.load) [load image, compression = lzss] 200010f3 00000001 --HOLE-- [fill = 0] 200010f4 0000000c (__TI_handler_table) 20001100 00000008 (.cinit..vtable_ram.load) [load image, compression = zero_init] 20001108 00000010 (__TI_cinit_table) .init_array * 0 20000000 00000000 UNINITIALIZED .ccfg 0 0001ffa8 00000058 0001ffa8 00000058 ccfg.obj (.ccfg:retain) .vtable_ram * 0 20001000 000000c8 UNINITIALIZED 20001000 000000c8 driverlib.lib : interrupt.obj (.vtable_ram) .data 0 200010c8 00000018 UNINITIALIZED 200010c8 0000000c rtsv7M3_T_le_eabi.lib : exit.obj (.data:$O1$$) 200010d4 00000008 : _lock.obj (.data:$O1$$) 200010dc 00000004 : stkdepth_vars.obj (.data) .stack 0 20004f00 00000100 UNINITIALIZED 20004f00 00000100 --HOLE-- .args 0 00000000 00000008 00000000 00000008 --HOLE-- [fill = 0] MODULE SUMMARY Module code ro data rw data ------ ---- ------- ------- ./ main.obj 650 0 0 startup_ccs.obj 22 200 0 ccfg.obj 0 88 0 +--+--------------------------+------+---------+---------+ Total: 672 288 0 /Applications/ti/ccsv7/tools/compiler/ti-cgt-arm_16.9.1.LTS/lib/rtsv7M3_T_le_eabi.lib memcpy_t2.obj 156 0 0 memset_t2.obj 122 0 0 autoinit.obj 112 0 0 copy_decompress_lzss.obj 104 0 0 exit.obj 84 0 12 cpy_tbl.obj 76 0 0 boot.obj 64 0 0 _lock.obj 20 0 8 args_main.obj 24 0 0 copy_decompress_none.obj 14 0 0 copy_zero_init.obj 12 0 0 pre_init.obj 4 0 0 stkdepth_vars.obj 0 0 4 mpu_init.obj 2 0 0 startup.obj 2 0 0 +--+--------------------------+------+---------+---------+ Total: 796 0 24 /Applications/ti/tirtos_cc13xx_cc26xx_2_20_01_08/products/cc13xxware_2_04_02_17240/driverlib/bin/ccs/driverlib.lib setup.obj 1842 0 0 interrupt.obj 52 0 200 chipinfo.obj 206 0 0 osc.obj 140 0 0 timer.obj 112 0 0 ddi.obj 44 0 0 cpu.obj 24 0 0 +--+--------------------------+------+---------+---------+ Total: 2420 0 200 Stack: 0 0 256 Linker Generated: 0 55 0 +--+--------------------------+------+---------+---------+ Grand Total: 3888 343 480 LINKER GENERATED COPY TABLES __TI_cinit_table @ 20001108 records: 2, size/record: 8, table size: 16 .data: load addr=200010e0, load size=00000013 bytes, run addr=200010c8, run size=00000018 bytes, compression=lzss .vtable_ram: load addr=20001100, load size=00000008 bytes, run addr=20001000, run size=000000c8 bytes, compression=zero_init LINKER GENERATED HANDLER TABLE __TI_handler_table @ 200010f4 records: 3, size/record: 4, table size: 12 index: 0, handler: __TI_zero_init index: 1, handler: __TI_decompress_lzss index: 2, handler: __TI_decompress_none GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name address name ------- ---- 200009f5 C$$EXIT 20000da1 ISR_TimerInterrupt_Handler 20000fc5 NOROM_CPUcpsid 20000fd1 NOROM_CPUcpsie 20000ae5 NOROM_ChipInfo_GetChipFamily 200006ad NOROM_ChipInfo_GetHwRevision 20000c41 NOROM_DDI32RegWrite 20000bad NOROM_IntRegister 20000c6d NOROM_OSCClockSourceGet 20000939 NOROM_OSCClockSourceSet 20000455 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 200001f9 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 200000c9 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 20000e59 NOROM_SetupGetTrimForAdcShModeEn 20000e71 NOROM_SetupGetTrimForAdcShVbufEn 200007fd NOROM_SetupGetTrimForAmpcompCtrl 20000e89 NOROM_SetupGetTrimForAmpcompTh1 20000dbd NOROM_SetupGetTrimForAmpcompTh2 20000869 NOROM_SetupGetTrimForAnabypassValue1 20000ea1 NOROM_SetupGetTrimForDblrLoopFilterResetVoltage 20000c99 NOROM_SetupGetTrimForRadcExtCfg 20000eb9 NOROM_SetupGetTrimForRcOscLfIBiasTrim 20000dd9 NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim 20000d45 NOROM_SetupGetTrimForXoscHfCtl 20000f69 NOROM_SetupGetTrimForXoscHfFastStart 20000f79 NOROM_SetupGetTrimForXoscHfIbiastherm 20000ed1 NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio 20000be1 NOROM_SetupSetAonRtcSubSecInc 20000a49 NOROM_SetupSetCacheModeAccordingToCcfgSetting 2000071d NOROM_SetupSetVddrLevel 20000fa9 NOROM_SetupSignExtendVddrTrimValue 200003b1 NOROM_SetupTrimDevice 20000f19 NOROM_ThisCodeIsBuiltForCC13xxHwRev20AndLater_HaltIfViolated 20000b2d NOROM_TimerIntRegister 20000f89 ResetISR UNDEFED SHT$$INIT_ARRAY$$Base UNDEFED SHT$$INIT_ARRAY$$Limit 20005000 __STACK_END 00000100 __STACK_SIZE 20005000 __STACK_TOP 20001108 __TI_CINIT_Base 20001118 __TI_CINIT_Limit 200010f4 __TI_Handler_Table_Base 20001100 __TI_Handler_Table_Limit 2000078d __TI_auto_init 200010c8 __TI_cleanup_ptr 200008d1 __TI_decompress_lzss 20000fb7 __TI_decompress_none 200010cc __TI_dtors_ptr 200010d0 __TI_enable_exit_profile_output ffffffff __TI_pprof_out_hndl ffffffff __TI_prof_data_size ffffffff __TI_prof_data_start 20000000 __TI_static_base__ 20000fe9 __TI_zero_init 20000631 __aeabi_memclr 20000631 __aeabi_memclr4 20000631 __aeabi_memclr8 20000595 __aeabi_memcpy 20000595 __aeabi_memcpy4 20000595 __aeabi_memcpy8 20000633 __aeabi_memset 20000633 __aeabi_memset4 20000633 __aeabi_memset8 ffffffff __binit__ 00000000 __c_args__ 0001ffa8 __ccfg 20000f2f __mpu_init 20004f00 __stack 20000f01 _args_main 20000b6d _c_int00 200010d4 _lock 20000f3f _nop 20000f37 _register_lock 20000f31 _register_unlock 20000f67 _system_post_cinit 20000ff5 _system_pre_init 200010d8 _unlock 200009f9 abort ffffffff binit 20000a99 copy_in 20000a01 exit 20001000 g_pfnRAMVectors 20000000 g_pfnVectors 20000999 led_setup 20000f99 main 200010dc main_func_sp 20000595 memcpy 20000639 memset 200004f5 timer_setup GLOBAL SYMBOLS: SORTED BY Symbol Address address name ------- ---- 00000000 __c_args__ 00000100 __STACK_SIZE 0001ffa8 __ccfg 20000000 __TI_static_base__ 20000000 g_pfnVectors 200000c9 NOROM_SetupAfterColdResetWakeupFromShutDownCfg3 200001f9 NOROM_SetupAfterColdResetWakeupFromShutDownCfg2 200003b1 NOROM_SetupTrimDevice 20000455 NOROM_SetupAfterColdResetWakeupFromShutDownCfg1 200004f5 timer_setup 20000595 __aeabi_memcpy 20000595 __aeabi_memcpy4 20000595 __aeabi_memcpy8 20000595 memcpy 20000631 __aeabi_memclr 20000631 __aeabi_memclr4 20000631 __aeabi_memclr8 20000633 __aeabi_memset 20000633 __aeabi_memset4 20000633 __aeabi_memset8 20000639 memset 200006ad NOROM_ChipInfo_GetHwRevision 2000071d NOROM_SetupSetVddrLevel 2000078d __TI_auto_init 200007fd NOROM_SetupGetTrimForAmpcompCtrl 20000869 NOROM_SetupGetTrimForAnabypassValue1 200008d1 __TI_decompress_lzss 20000939 NOROM_OSCClockSourceSet 20000999 led_setup 200009f5 C$$EXIT 200009f9 abort 20000a01 exit 20000a49 NOROM_SetupSetCacheModeAccordingToCcfgSetting 20000a99 copy_in 20000ae5 NOROM_ChipInfo_GetChipFamily 20000b2d NOROM_TimerIntRegister 20000b6d _c_int00 20000bad NOROM_IntRegister 20000be1 NOROM_SetupSetAonRtcSubSecInc 20000c41 NOROM_DDI32RegWrite 20000c6d NOROM_OSCClockSourceGet 20000c99 NOROM_SetupGetTrimForRadcExtCfg 20000d45 NOROM_SetupGetTrimForXoscHfCtl 20000da1 ISR_TimerInterrupt_Handler 20000dbd NOROM_SetupGetTrimForAmpcompTh2 20000dd9 NOROM_SetupGetTrimForRcOscLfRtuneCtuneTrim 20000e59 NOROM_SetupGetTrimForAdcShModeEn 20000e71 NOROM_SetupGetTrimForAdcShVbufEn 20000e89 NOROM_SetupGetTrimForAmpcompTh1 20000ea1 NOROM_SetupGetTrimForDblrLoopFilterResetVoltage 20000eb9 NOROM_SetupGetTrimForRcOscLfIBiasTrim 20000ed1 NOROM_SetupGetTrimForXoscLfRegulatorAndCmirrwrRatio 20000f01 _args_main 20000f19 NOROM_ThisCodeIsBuiltForCC13xxHwRev20AndLater_HaltIfViolated 20000f2f __mpu_init 20000f31 _register_unlock 20000f37 _register_lock 20000f3f _nop 20000f67 _system_post_cinit 20000f69 NOROM_SetupGetTrimForXoscHfFastStart 20000f79 NOROM_SetupGetTrimForXoscHfIbiastherm 20000f89 ResetISR 20000f99 main 20000fa9 NOROM_SetupSignExtendVddrTrimValue 20000fb7 __TI_decompress_none 20000fc5 NOROM_CPUcpsid 20000fd1 NOROM_CPUcpsie 20000fe9 __TI_zero_init 20000ff5 _system_pre_init 20001000 g_pfnRAMVectors 200010c8 __TI_cleanup_ptr 200010cc __TI_dtors_ptr 200010d0 __TI_enable_exit_profile_output 200010d4 _lock 200010d8 _unlock 200010dc main_func_sp 200010f4 __TI_Handler_Table_Base 20001100 __TI_Handler_Table_Limit 20001108 __TI_CINIT_Base 20001118 __TI_CINIT_Limit 20004f00 __stack 20005000 __STACK_END 20005000 __STACK_TOP ffffffff __TI_pprof_out_hndl ffffffff __TI_prof_data_size ffffffff __TI_prof_data_start ffffffff __binit__ ffffffff binit UNDEFED SHT$$INIT_ARRAY$$Base UNDEFED SHT$$INIT_ARRAY$$Limit [90 symbols]
Finally here is the source to the simple program that I made, all located in main.c
/*
* main.c
*/
#include <stdint.h>
#include <stdbool.h>
#include <boot_loader.h>
#include "driverlib/gpio.h"
#include "driverlib/ioc.h"
#include "driverlib/prcm.h"
#include "driverlib/timer.h"
#include "driverlib/sys_ctrl.h"
#include "inc/hw_memmap.h"
#include "inc/hw_ints.h"
void led_setup(void);
void ISR_TimerInterrupt_Handler(void);
void timer_setup(void);
/*
* ======== main ========
* Main function
*/
int main(void) {
// setup the LEDs
led_setup();
// setup the timer
timer_setup();
// enable the master interrupt
IntMasterEnable();
// loop forever waiting for an interrupt
for(;;);
if (bootloaderOpened())
{
// Choose between SPI and UART, and do baud rate detection for UART
PickInterface();
// Boot loader control loop. Does not return.
Update();
}
else
{
// Change the below constant to match the application image intvec start.
// vvvvvv
asm(" MOV R0, #0x1010 "); // The .resetVecs or .intvecs for the app are
// are placed at the constant #0xXXXX address
asm(" LDR SP, [R0, #0x0] "); // Load the initial stack pointer
asm(" LDR R1, [R0, #0x4] "); // Load the Reset vector address
asm(" BX R1 "); // Jump to the application Reset vector
}
return 0;
}
/*
* ======== led_setup ========
* Setup the red and green LEDs
*/
void led_setup(void)
{
// Power on periperal domain
PRCMPowerDomainOn(PRCM_DOMAIN_PERIPH);
while(PRCMPowerDomainStatus(PRCM_DOMAIN_PERIPH) != PRCM_DOMAIN_POWER_ON);
// Power on the GPIO peripheral
PRCMPeripheralRunEnable(PRCM_PERIPH_GPIO);
PRCMLoadSet();
while ( !PRCMLoadGet() );
// enable output for the red LED
GPIO_setOutputEnableDio(IOID_6, GPIO_OUTPUT_ENABLE);
// turn on the red LED
GPIO_setDio(IOID_6);
// enable output for the green LED
GPIO_setOutputEnableDio(IOID_7, GPIO_OUTPUT_ENABLE);
//turn off the green LED
GPIO_clearDio(IOID_7);
}
/*
* ======== ISR_TimerInterrupt_Handler ========
* Interrupt handler to service the TIMER_TIMA_TIMEOUT interrupt.
*/
void ISR_TimerInterrupt_Handler(void)
{
// clear interrupt flag
TimerIntClear(GPT0_BASE, TIMER_TIMA_TIMEOUT);
// toggle the red LED
GPIO_toggleDio(IOID_6);
// toggle the green LED
GPIO_toggleDio(IOID_7);
}
/*
* ======== timer_setup ========
* Function to setup the GPT0 timer.
* Using GPT0 timer A, periodic mode
* Interrupt callback to ISR_TimerInterrupt_Handler
*/
void timer_setup(void)
{
// Power on periperal domain
PRCMPowerDomainOn(PRCM_DOMAIN_PERIPH);
PRCMLoadSet();
while ( !PRCMLoadGet() );
// Power on the TIMER0 peripheral
PRCMPeripheralRunEnable(PRCM_PERIPH_TIMER0);
PRCMLoadSet();
while ( !PRCMLoadGet() );
// Enable TIMER0 to continue counting while the MCU sleeps
PRCMPeripheralSleepEnable(PRCM_PERIPH_TIMER0);
// Configure the TIMER0
TimerConfigure(GPT0_BASE, TIMER_CFG_A_PERIODIC);
// Set initial timer value
TimerLoadSet(GPT0_BASE, TIMER_A, 0xFFFFFF);
// Set prescaler
TimerPrescaleSet(GPT0_BASE, TIMER_A, 0x000000FF);//255
// Timer to count on positive clock edge
TimerEventControl(GPT0_BASE,TIMER_A,TIMER_EVENT_POS_EDGE);
// Be sure the interrupt is clear to start
TimerIntClear(GPT0_BASE,TIMER_TIMA_TIMEOUT);
// Assign the interrupt handler
TimerIntRegister(GPT0_BASE, TIMER_A, ISR_TimerInterrupt_Handler);
// Enable the interrupt
TimerIntEnable(GPT0_BASE,TIMER_TIMA_TIMEOUT);
// Enable the timer
TimerEnable(GPT0_BASE,TIMER_A);
}
I think I have narrowed down the issue, but I am not sure how to fix it yet...
As stated in the DriverLib/interrupt.h file...
//***************************************************************************** // //! \brief Registers a function to be called when an interrupt occurs. //! //! This function is used to specify the handler function to be called when the //! given interrupt is asserted to the processor. When the interrupt occurs, //! if it is enabled (via \ref IntEnable()), the handler function will be called in //! interrupt context. Since the handler function can preempt other code, care //! must be taken to protect memory or peripherals that are accessed by the //! handler and other non-handler code. //! //! \note The use of this function (directly or indirectly via a peripheral //! driver interrupt register function) moves the interrupt vector table from //! flash to SRAM. Therefore, care must be taken when linking the application //! to ensure that the SRAM vector table is located at the beginning of SRAM; //! otherwise NVIC will not look in the correct portion of memory for the //! vector table (it requires the vector table be on a 1 kB memory alignment). //! Normally, the SRAM vector table is so placed via the use of linker scripts. //! //! \param ui32Interrupt specifies the interrupt in question. //! \param pfnHandler is a pointer to the function to be called. //! //! \return None. // //***************************************************************************** extern void IntRegister(uint32_t ui32Interrupt, void (*pfnHandler)(void)); //*****************************************************************************
Therefore the following should be located at the top of SRAM...
20000000 g_pfnRAMVectors
But, after what I did to relocate everything to SRAM is appears to be located at...
20001000 g_pfnRAMVectors
I believe this is throwing off the interrupt vector table, and still not sure what to do to move it up...
Really, it does not need to be relocated as it is in SRAM already, simply disabling the relocation code might work... it appears to be in ROM though, not able to be changed?
Someone with more knowledge about how the interrupt vector table relocation logic works might be able to give me a clue as to how I should proceed?
AllanD
I have created a new thread to address the SRAM interrupt issue, it is located here since this thread is beginning to stray from the original topic.
LAUNCHXL-CC1350: Interrupts fail to fire when executing application from SRAM