CC2640R2F: Cache as ram FAIL,in simple_peripheral_oad_offchip,urgent!!!!!

Hello,

The attached linker file looks good, however I believe the issue may be related to the CCFG.

In OAD designs, the CCFG is linked as part of the BIM project and isn't included in the application.
Using Cache as RAM with OAD will require you to rebuild the BIM with the new CCFG that enables cache as ram.

@Sean2 , this issue is the same as e2e.ti.com/.../595413 and I don't think it is related to BIM. Have you tried it?

Hello teddy,

Does your map file show the .bss section being placed in the GPRAM region?

Can you also update your icf file to have this modification (same as used in BLE5-Stack in SDK 1.35):

if ( isdefinedsymbol(CACHE_AS_RAM) )
{
// GPRAM
define block GPDATA { section .bss };
place in GPRAM { block GPDATA } except{ object ll.o };
}

The 'except' bit is important.

Best wishes

I am working to reproduce it now.

However, based on the OAD design this will require a re-build of BIM since the cache as RAM configuration requires changes to the CCFG and the BIM is the project that links the CCFG. OAD applications are not designed to link the CCFG.

JXS  I tried to put your modification about except bit into icf but it still doesn't work.

Sean2  I just download cc2640r2_stack to LAUNCHXL-CC2640R2 first and download/debug cc2640r2_app from IAR. I don't download BIM. When I don't enable CACHE_AS_RAM, it can debug and trace cc2640r2_app. After I enable  CACHE_AS_RAM, it pops the following error when I download/debyg cc2640r2_app from IAR. I don't think this is related to BIM. Can you reproduce it in your environment? Do you have other solution?

Hello JXS.

  i try it with your solution.but it still not run.

Can someone give solutions? @Ti guys

Sean2 ,JXS ,YiKai Chen .

I tried another LAUNCHXL-CC2640R2 that I borrow it from distributor and it works. I suspect it is HW related.

I try it on two LAUNCHXL-CC2640R2.both are fail. not understand

Color of LAUNCHXL-CC2640R2 from distributor looks different to my LAUNCHXL-CC2640R2 but the HW version is the same. I don't know why it works but mine not. Hope someone from TI can verify this.

no answer

It seems no one from TI can help on this.

We are still looking into this.

Question: Did you modify the CCFG in the BIM to enable cache as RAM as @Sean2 advised?

Best wishes

This example doesn't use BIM why I have to change CCFG in BIM?

Aren't we talking about the simple_peripheral_oad_offchip sample application? See Step #1 of the "Using IAR" in the SDG: software-dl.ti.com/.../oad.html

"Open the bim_oad_offchip project, build and load it onto the CC2640R2 Launchpad using the debugger."

Best wishes

The problem occurs when I debug simple_peripheral_oad_offchip using IAR. Do I still have to use BIM when I download/debug with IAR? The strange thing is that why I can make it work on another board from distributor but not on my own one even the board version is the same.

JXS I try to do steps in software-dl.ti.com/.../platform.html to bim_oad_offchip project but i get the following build error.

unable to allocate space for sections/blocks with a total estimated minimum size of 0x1220 bytes (max align 0x4) in <[0x0001f000-0x0001ffff]> (total uncommitted space 0xee0).

YiKai Chen I'm not sure why you get the link error. Can you try a clean SDK install? Also, does the LaunchPad from the distributor have a BIM already programmed? You can also check the VIMS setting of the cache to confirm it's in GPRAM mode.

Just to be clear on the steps:

The BIM is the first executable and needs to convert the cache to GPRAM via CCFG. If this doesn't occur the simple_peripheral application will attempt to access GPRAM as .bss but it won't exist which will lead to bad things (read: dragons)

The remaining changes under CACHE_AS_RAM need to be applied to the simpe_peripheral off chip oad project, including the linker.

Best wishes

@JXS After I use bim_oad_offchip project, it works. Thanks.

YiKai Chen ,
can you show more detail message.thanks