This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Unexplained Junk in CC110L Receive FIFO

Other Parts Discussed in Thread: CC110L, TEST2

Hi All,

I am attempting to RF link between a Stellaris launchpad (EK-LM4F120XL) and the new Tiva connected launchpad (EK-TM4C129XL) using a pair of CC110L AIR Boosterpacks. I went about writing my own libraries from scratch for the hell of it and it is nearly 100% working (working directly from the CC110L data sheet).

Both boards can read/write to the CC110L's config and status registers with no issue.

The issue is that I seem to get an incredible amount of junk in my receiver side RX FIFO. If this were purely random I would assume I had just gone wrong somewhere but I can see that the original packet transmitted is in the FIFO along with the junk.

The first packet sent by the transmitter is received perfectly but after that the RX FIFO seems to get flooded. 

I keep reading that Smart RF should be used to get the ideal register settings for the CC110L. How does one go about this with the AIR Boosterpacks ? (if possible). I have opened Smart RF and selected the CC110L and used some of the  default reg settings listed there but I must admit I went a bit cross-eyed when the data sheet started talking about the "RF" aspects (LNA currents etc.).

The Register settings I am using are as follows:

 

                    CC110L_IOCFG2,   0x29 // GDO2 output pin config.`CHIP_RDYn
		    CC110L_IOCFG1,   0x2E // GDO1 output pin config.`HIGH IMP
		    CC110L_IOCFG0,   0x06 // GDO0 output pin config.`sync high on rx and tx
		    CC110L_FIFOTHR,  0x07 // THR.`32 bytes RX ; 33 bytes TX fifo
		    CC110L_SYNC1,    0xD3 // Packet automation control.`
		    CC110L_SYNC0,    0x91 // Packet automation control.`
		    CC110L_PKTLEN,   0xFF // Packet length.`
		    CC110L_PKTCTRL1, 0x0D // `flush when CRC not ok , Append Enabled .. Address Check Enabled
		    CC110L_PKTCTRL0, 0x05 // `normal mode ,CRC enabled , variable packet length
		    CC110L_ADDR,     0x33 // Device address.` 0x33 is arbitrary (TX side sends to this addr) 
		    CC110L_CHANNR,   0x80 // Channel number. 
		    CC110L_FSCTRL1,  0x0C // Freq synthesizer control.`..2
		    CC110L_FSCTRL0,  0x00
		    CC110L_FREQ2,    0x21 // Freq control word, high byte`
		    CC110L_FREQ1,    0x62 // Freq control word, mid byte.`
		    CC110L_FREQ0,    0x76 // Freq control word, low byte.`
		    CC110L_MDMCFG4,  0xEA // Modem configuration.` => From Smart RF Default 
		    CC110L_MDMCFG3,  0x71 // Modem configuration.`
		    CC110L_MDMCFG2,  0x13 // Modem configuration.`
		    CC110L_MDMCFG1,  0x20 // Modem configuration.`
		    CC110L_MDMCFG0,  0xF8 // Modem configuration.`
		    CC110L_DEVIATN,  0x33 // Modem dev (when FSK mod en)`??
		    CC110L_MCSM2,    0x07 //MainRadio Cntrl State Machine`
		    CC110L_MCSM1 ,   0x3F //MainRadio Cntrl State Machine`stay in tx
		    CC110L_MCSM0 ,   0x18 //MainRadio Cntrl State Machine`
		    CC110L_FOCCFG,   0x16 // Freq Offset Compens. Config`??
		    CC110L_BSCFG,    0x6C //  Bit synchronization config.`??
		    CC110L_AGCCTRL2, 0x43 // AGC control.`
		    CC110L_AGCCTRL1, 0x4F // AGC control.`
		    CC110L_AGCCTRL0, 0x91 // AGC control.`
		    CC110L_WOREVT1,  0x00 // WOR ??
		    CC110L_WOREVT0,  0x00 // WOR ??
		    CC110L_WORCTRL,  0xF8 // WOR ??
		    CC110L_FREND1,   0x56 // Front end RX configuration.`
		    CC110L_FREND0,   0x10 // Front end RX configuration.`
		    CC110L_FSCAL3,   0xE9 // Frequency synthesizer cal.`
		    CC110L_FSCAL2,   0x2A // Frequency synthesizer cal.`
		    CC110L_FSCAL1,   0x00 // Frequency synthesizer cal.`
		    CC110L_FSCAL0,   0x1F // Frequency synthesizer cal.`
		    CC110L_RCCTRL1,  0x00 // Packet automation control.`
		    CC110L_RCCTRL0,  0x00 // Packet automation control.`
		    CC110L_FSTEST,   0x59 // Frequency synthesizer cal.
		    CC110L_PSTEST,   0x7F // Frequency synthesizer cal.
		    CC110L_AGCTEST,  0x3F // Frequency synthesizer cal.
		    CC110L_TEST2,    0x81 // Various test settings.`
		    CC110L_TEST1,    0x35 // Various test settings.`
		    CC110L_TEST0,    0x09 // Various test settings.`

The same settings are used on both ends (Rx and TX) with the exception of the device Address.  

After messing around for roughtly 200 years I just decided to output the entire RX FIFO when GDO0 triggers an interrupt (Setting IOCFG0= 0x06 .. asserts when sync byte is seen).

The following is a typical output:

NOTE: Bytes being transmitted are  "7 , 51 , 2 , 4 , 6 , 2 ,4 ,6 " periodically

Where '7' is the packet length field , and '51' is the address (0x33 above)

So we expect the Rx FIFO to contain 51 , 2 , 4 , 6 , 2 ,4 ,6 

First Transmission:

ISR TRIGGERED 
,Rx Fifo : 51 2 4 6 2 4 8
Leaving ISR 

// ALL FINE WITH THIS ONE !

Second Transmission:

ISR TRIGGERED 1
,Rx Fifo : 171 7 51 2 4 6 2 4 8 85 167 167 95 162 58 192 6 207 183 193 7 209 55 161 184 81 211 33 210 251 118 93 188 152 238 91 172 169 10 45 42 215 164 122 109 206 52 158 190 11 139 218 159 255 74 165 191 51 2 4 6 2 4 8 80 171 7 51 2 4 6 2 4 8 85 167 95 162 58 192
Leaving ISR 

And from there on the junk is consistently present, sometimes the original packet isn't even in the RX FIFO, i.e. the ISR was triggered by junk. 

NOTE: I release the appended bytes (in green above) are meant to be there as they are the LQI and RSSI info.

I'm lost for what to try next so if anyone has any ideas I would greatly appreciate it !

Sorry about the post length

Regards,

Jay Long 

 

  • Hi

    I will also advise you to use SmartRF Studio for your register settings. There is no need for you to spend time on reading all the register descriptions and try to figure this out yourself when we have had several people using many months on optimizing the settings for you.

    Select one of the typical settings close to the data rate you want to transmit on do a code export. If selecting 38.4 kBaud you will get the following settings when doing the code export:

     

    // Channel spacing = 199.951172

    // Sync word qualifier mode = 30/32 sync word bits detected

    // Packet length = 255

    // Preamble count = 4

    // RX filter BW = 101.562500

    // Carrier frequency = 867.999939

    // Packet length mode = Variable packet length mode.  

    // Data format = Normal mode

    // CRC autoflush = false

    // Address config = No address check

    // CRC enable = true

    // Data rate = 38.3835

    // TX power = 0

    // Manchester enable = false

    // Base frequency = 867.999939

    // Deviation = 20.629883

    // Modulation format = GFSK

    // Modulated = true

    // Device address = 0

     

    static const registerSetting_t preferredSettings[]=

    {

    {CC110L_IOCFG0, 0x06},

    {CC110L_FIFOTHR, 0x47},

    {CC110L_PKTCTRL0, 0x05},

    {CC110L_FSCTRL1, 0x06},

    {CC110L_FREQ2, 0x21},

    {CC110L_FREQ1, 0x62},

    {CC110L_FREQ0, 0x76},

    {CC110L_MDMCFG4, 0xCA},

    {CC110L_MDMCFG3, 0x83},

    {CC110L_MDMCFG2, 0x13},

    {CC110L_DEVIATN, 0x35},

    {CC110L_MCSM0, 0x18},

    {CC110L_FOCCFG, 0x16},

    {CC110L_AGCCTRL2, 0x43},

    {CC110L_RESERVED_0X20, 0xFB},

    {CC110L_FSCAL3, 0xE9},

    {CC110L_FSCAL2, 0x2A},

    {CC110L_FSCAL1, 0x00},

    {CC110L_FSCAL0, 0x1F},

    {CC110L_TEST2, 0x81},

    {CC110L_TEST1, 0x35},

    {CC110L_TEST0, 0x09},

    };

     

    Use these settings as is and see that you get the code up and running now. This code use RXOFF_MODE = TXOFF_MODE = IDLE, CRC enabled, variable packet length, append status bytes enabled.

    When you get a falling edge interrupt on GDO0 you need to check that there is no RXFIFO_OVERFLOW before reading the packet. To avoid getting overflow you can enable packet length filtering by setting PKTLEN <= 61.

    When reading the FIFO it is important that you read out the status bytes also so they will not be left in there.

    When enabling address filtering you must in addition remember to check that the FIFO is not empty when you get an interrupt in case the packet has been filtered away (you should never try to read an empty FIFO).

    When all this works you can try to implement one and one change to the registers to get exactly what you want when it comes to packet format etc.

    Below is some code that will work on the receiver when an interrupt has occurred:

    cc11xLSpiReadReg (CC110L_RXBYTES, &rxBytes, 1);

    // Check that we have bytes in FIFO

    if(rxBytes != 0) {

      // Read MARCSTATE to check for RX FIFO error

      cc11xSpiReadReg(CC110L_MARCSTATE, &marcState, 1);

      // Mask out MARCSTATE bits and check if we have a RX FIFO error

      if((marcState & 0x1F) == RX_FIFO_ERROR) {

        // Flush RX FIFO

        trxSpiCmdStrobe(CC110L_SFRX);

      } else {

        // Read n bytes from RX FIFO

        cc11xLSpiReadRxFifo(rxBuffer, rxBytes);

        // Check CRC ok (CRC_OK: bit7 in second status byte)

        // This assumes status bytes are appended in RX_FIFO

        // (PKTCTRL1.APPEND_STATUS = 1)

        // If CRC is disabled the CRC_OK field will read 1

        if(rxBuffer[rxBytes - 1] & 0x80) {

          // Update packet counter

          packetCounter++;

        }

      }

    }

     

    Siri 

  • Siri, Thanks for the quick and helpful reply!

    I will take this on board and post an update and verify solution. 

    Am I correct in saying that I will need two CC Debugger tools to use Smart RF on my two AIR Boosterpacks ?

    Thanks again,

    Regards,

    Jay Long

  • Hi

    You do not have to run Studio on the boards. Just use Studio (you can do this in offline mode) to generate the settings and then copy the settings into your code.

    Siri