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CC1200 SPI timing

Darren Wang1
Prodigy 50 points
Other Parts Discussed in Thread: CC1200

I'm looking for clarification of datasheet description, specifically note on pg.7 table 1 from

http://www.ti.com/lit/ug/swru346b/swru346b.pdf

Am I understanding correctly that the "100 ns delay between consecutive data bytes ... during burst write" is as below?

8 cycles SCLK -> 100 ns delay -> 8 cycles SCLK -> 100 ns delay ... 

Thanks

  • 0
    TI__Mastermind 36375 points

    Darren, 

    Yes, your understanding is correct. The CC1200 needs a 100ns to move the data internally. Generally using MSP430 or other low power MCU this is not a problem because the overall clock speed of the host system is slow enough that these timings will always be upheld. The only time we see this issue come up is if someone attaches the CC1200 or similar product to a 100MHz+ MCU/MPU.

    Good luck with your project.

    Regards,
    /TA