Why changes the MAX_DVGA_GAIN[1:0] setting in CC430F5133 can not affect the RSSI value?

What do you want to achieve by adjusting the gain?

I understand what you want to use it for but not sure why you are trying to adjust these registers.

thanks for your reply,

actually, We want to control the RF distance by changing the LNA gain, that is the RSSI
threshold, but setting the  MAX_DVGA_GAIN value seems no effect to the RSSI,  no matter changes the value of MAZ_DVGA_GAIN to 00,01,10,11, still same RSSI I got. Only if changes the LNA_GAIN got a obvious difference of RSSI. Thus, how to handle the MAX_DVGA_GAIN?

Need your help for this issue, thank you. 

The DVGA is not a gain block as such, it just selects 10 bit out of total 17 bit, the setting controls which 10 bit.

RF distance, do you want to be able to get correct RSSI for high input levels (as described here: http://www.ti.com/lit/an/swra147b/swra147b.pdf) or what do you mean by "control RF distance"/ "RSSI threshold"?

Hi,

Customer is trying to use such parameter to restrict the communication distance, such like the receiver is only allow to receive the high signal strength to have short distance, they want to control this by HW detector instead of firmware code to reject the higher RSSI packet.

Gary Lin

If that is the case, why not use Carrier Sense?

Hi,

Yes, this is what we want. We found out that have to change those value to change the threshold, we didn't success so that's why we raised out the question.

Could you confirm that MDMCFG2.SYNC_MODE is set larger than 0x5?

yes, we set the MDMCFG2.SYNC_MODE larger than 0x05, but the RSSI value still not change too much no matter setting the MAX_DVGA_GAIN to 00,01,10,11.

AGCCTRL2 set to 0x3b and 0xfb,  the RSSI value still between -90dBm ~ -95dBm, still not meet  -61 ~-79dBm described in userguide.

The test environment is smartRF studio7, set 2.4k data rate, 868MHz,

Please post the SmartRF Studio xml file (file -> save config) in SmartRF Studio)

here is the file:

// Rf settings for CC430F5137
RF_SETTINGS code rfSettings = {
    0x0B,  // IOCFG2          GDO2 Output Configuration
    0x0C,  // IOCFG0          GDO0 Output Configuration
    0x47,  // FIFOTHR         RX FIFO and TX FIFO Thresholds
    0x12,  // PKTCTRL0        Packet Automation Control
    0x0A,  // CHANNR          Channel Number
    0x06,  // FSCTRL1         Frequency Synthesizer Control
    0x21,  // FREQ2           Frequency Control Word, High Byte
    0x62,  // FREQ1           Frequency Control Word, Middle Byte
    0x76,  // FREQ0           Frequency Control Word, Low Byte
    0xF6,  // MDMCFG4         Modem Configuration
    0x83,  // MDMCFG3         Modem Configuration
    0x15,  // MDMCFG2         Modem Configuration
    0x15,  // DEVIATN         Modem Deviation Setting
    0x10,  // MCSM0           Main Radio Control State Machine Configuration
    0x16,  // FOCCFG          Frequency Offset Compensation Configuration
    0xFB,  // AGCCTRL2        AGC Control
    0x41,  // AGCCTRL1        AGC Control
    0x87,  // WOREVT1         High Byte Event0 Timeout
    0x6B,  // WOREVT0         Low Byte Event0 Timeout
    0xFB,  // WORCTRL         Wake On Radio Control
    0xE9,  // FSCAL3          Frequency Synthesizer Calibration
    0x2A,  // FSCAL2          Frequency Synthesizer Calibration
    0x00,  // FSCAL1          Frequency Synthesizer Calibration
    0x1F,  // FSCAL0          Frequency Synthesizer Calibration
    0x81,  // TEST2           Various Test Settings
    0x35,  // TEST1           Various Test Settings
    0x09,  // TEST0           Various Test Settings
    0x80,  // RSSI            Received Signal Strength Indication
    0x94,  // VCO_VC_DAC      Current Setting from PLL Calibration Module
};

I did some measurements in the weekend (see attached excel sheet for settings and the results) and based on my measurements the chip behaves like expected based on the datasheet

PER_vs_level.xlsx

Did you test with the settings provided in the excel sheet I posted?

As my results shows I get the same results as in the datasheet