Hello,
I need clarification of Design Note DN106 (Power Modes in CC111xFx...).
In DN106 is part that is described as time critical and is noted that should be done without intervening code. In that part following tasks are done:
- Align with positive 32 kHz clock
- Disable Flash cache
- Set SLEEP reg (choose power mode)
- Three NOPs (waiting for SLEEP to take effect - after which interrupts are disabled)
- check SLEEP reg - if interrupt happened during Three NOPs system will skip entering Power mode
- Activation of Power mode (with DMA transfer activation)
Things that are troubling me:
- In order to follow minimum sleep time requirement I must ensure that there is enough time before entering PM. That means that I must ensure no interrupts will 'steal' time from me after checking sleep time and before entering PM (lets say ISR processing time can't be ignored).
- what will happen if pin interrupt is happen just after alignment with positive 32 kHz clock? In that case entering PM will not be aligned any more. That case is not covered within DN106.
To solve those issues I've disabled global interrupt before minimum sleep time req calculation and then reenabled EA after three NOPs. Is that safe or not? I'm reasoning that after setting SLEEP and after three NOPs interrupts are disabled (described in datasheet).
In that solution I can observe problem (once per couple of days) of Sleep Timer switch to slower rate. That is manifestation of 32 kHz clock edge misalignment during entering sleep (128x Sleep Timer slow down). I'm not sure do I have problem somewhere else but I want to be sure what is safe to do regarding DN106.
If I should not tamper proposed code in Design Note at all then what is solution to described problems?
Thank you for your help,
Luka
