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RSSI values using CC2500 + MSP430f1232

I have a board using CC2500 and MSP430F1232 , sending wireless packets using RF. This board is configured in the TX (TRANSMIT) mode and successfully  transmits information every 6 seconds (i am transmitting at zero dbm level- which is almost the highest power level i can transmit information in). There exists another board using CC2500 AND MSP430F1232, waiting to receive packets. I intend to transmit and receive packets in a room with 20m * 20m area. I have followed all the necessary steps required to implement the board in the receive mode, but i do not get any interrupt on receive. The pin 0 on port 0 has been configured to interrupt on the falling edge. Can anyone help me spot the problem? i have used the following settings and my source code is attached.

PORT SETTINGS:-

// --- CC2500 Interface ---
// P1.0 <-- GDO-0 (int)
// P1.1 <-- GDO-2 (int)
// P1.2 --> CSN-CC2500                                          
// P1.3 --> CSEEPROM
// P1.4 --> WPEEPROM
// P1.5 --> UCLK
// P1.6 --> SIMO
// P1.7 --> SOMI

NECESSARY REGISTER SETTINGS:-

IOCFG2 = 0x29 (GDO-2 will be used as default to signal CHPRDY (chip ready))

IOCFG0 = 0x06 (GDO-0 asserted-low when packet received)

PKTLEN = 0x10 (Packet length is 16 bytes)

PKTCTRL1 = 0x00

PKTCTRL0 = 0x84

FREND1 = 0xB6 (Front end RX configuration.)

MCSM1 = 0x00 (return to idle after completing RX)

-------------------------------------------------------------------------------------------------------

SOURCE CODE :-

/*******************************************************************************
*
* File              cc2500_TagRx.c
* Description       TAGRx implementation for CC2500 & MSP430
*
*
*******************************************************************************///******************************************************************************
//  CC2500 TAG-RX Test Code - March 2008
//
// 
//                MSP430F2012
//               ------------
//
// --- CC2500 Interface ---
// P1.0 <-- GDO-0 (int)
// P1.1 <-- GDO-2 (int)
// P1.2 --> CSN-CC2500                                          
// P1.3 --> CSEEPROM
// P1.4 --> WPEEPROM
// P1.5 --> UCLK
// P1.6 --> SIMO
// P1.7 --> SOMI
//

//******************************************************************************
#include  "msp430x20x2.h"

//-------------------------------
// CC2500 defines
//-------------------------------


// Configuration Registers
#define TI_CCxxx0_IOCFG2       0x00        // GDO2 output pin configuration
#define TI_CCxxx0_IOCFG1       0x01        // GDO1 output pin configuration
#define TI_CCxxx0_IOCFG0       0x02        // GDO0 output pin configuration
#define TI_CCxxx0_FIFOTHR      0x03        // RX FIFO and TX FIFO thresholds
#define TI_CCxxx0_SYNC1        0x04        // Sync word, high byte
#define TI_CCxxx0_SYNC0        0x05        // Sync word, low byte
#define TI_CCxxx0_PKTLEN       0x06        // Packet length
#define TI_CCxxx0_PKTCTRL1     0x07        // Packet automation control
#define TI_CCxxx0_PKTCTRL0     0x08        // Packet automation control
#define TI_CCxxx0_ADDR         0x09        // Device address
#define TI_CCxxx0_CHANNR       0x0A        // Channel number
#define TI_CCxxx0_FSCTRL1      0x0B        // Frequency synthesizer control
#define TI_CCxxx0_FSCTRL0      0x0C        // Frequency synthesizer control
#define TI_CCxxx0_FREQ2        0x0D        // Frequency control word, high byte
#define TI_CCxxx0_FREQ1        0x0E        // Frequency control word, middle byte
#define TI_CCxxx0_FREQ0        0x0F        // Frequency control word, low byte
#define TI_CCxxx0_MDMCFG4      0x10        // Modem configuration
#define TI_CCxxx0_MDMCFG3      0x11        // Modem configuration
#define TI_CCxxx0_MDMCFG2      0x12        // Modem configuration
#define TI_CCxxx0_MDMCFG1      0x13        // Modem configuration
#define TI_CCxxx0_MDMCFG0      0x14        // Modem configuration
#define TI_CCxxx0_DEVIATN      0x15        // Modem deviation setting
#define TI_CCxxx0_MCSM2        0x16        // Main Radio Cntrl State Machine config
#define TI_CCxxx0_MCSM1        0x17        // Main Radio Cntrl State Machine config
#define TI_CCxxx0_MCSM0        0x18        // Main Radio Cntrl State Machine config
#define TI_CCxxx0_FOCCFG       0x19        // Frequency Offset Compensation config
#define TI_CCxxx0_BSCFG        0x1A        // Bit Synchronization configuration
#define TI_CCxxx0_AGCCTRL2     0x1B        // AGC control
#define TI_CCxxx0_AGCCTRL1     0x1C        // AGC control
#define TI_CCxxx0_AGCCTRL0     0x1D        // AGC control
#define TI_CCxxx0_WOREVT1      0x1E        // High byte Event 0 timeout
#define TI_CCxxx0_WOREVT0      0x1F        // Low byte Event 0 timeout
#define TI_CCxxx0_WORCTRL      0x20        // Wake On Radio control
#define TI_CCxxx0_FREND1       0x21        // Front end RX configuration
#define TI_CCxxx0_FREND0       0x22        // Front end TX configuration
#define TI_CCxxx0_FSCAL3       0x23        // Frequency synthesizer calibration
#define TI_CCxxx0_FSCAL2       0x24        // Frequency synthesizer calibration
#define TI_CCxxx0_FSCAL1       0x25        // Frequency synthesizer calibration
#define TI_CCxxx0_FSCAL0       0x26        // Frequency synthesizer calibration
#define TI_CCxxx0_RCCTRL1      0x27        // RC oscillator configuration
#define TI_CCxxx0_RCCTRL0      0x28        // RC oscillator configuration
#define TI_CCxxx0_FSTEST       0x29        // Frequency synthesizer cal control
#define TI_CCxxx0_PTEST        0x2A        // Production test
#define TI_CCxxx0_AGCTEST      0x2B        // AGC test
#define TI_CCxxx0_TEST2        0x2C        // Various test settings
#define TI_CCxxx0_TEST1        0x2D        // Various test settings
#define TI_CCxxx0_TEST0        0x2E        // Various test settings

// Strobe commands
#define TI_CCxxx0_SRES         0x30        // Reset chip.
#define TI_CCxxx0_SFSTXON      0x31        // Enable/calibrate freq synthesizer
#define TI_CCxxx0_SXOFF        0x32        // Turn off crystal oscillator.
#define TI_CCxxx0_SCAL         0x33        // Calibrate freq synthesizer & disable
#define TI_CCxxx0_SRX          0x34        // Enable RX.
#define TI_CCxxx0_STX          0x35        // Enable TX.
#define TI_CCxxx0_SIDLE        0x36        // Exit RX / TX
#define TI_CCxxx0_SAFC         0x37        // AFC adjustment of freq synthesizer
#define TI_CCxxx0_SWOR         0x38        // Start automatic RX polling sequence
#define TI_CCxxx0_SPWD         0x39        // Enter pwr down mode when CSn goes hi
#define TI_CCxxx0_SFRX         0x3A        // Flush the RX FIFO buffer.
#define TI_CCxxx0_SFTX         0x3B        // Flush the TX FIFO buffer.
#define TI_CCxxx0_SWORRST      0x3C        // Reset real time clock.
#define TI_CCxxx0_SNOP         0x3D        // No operation.

// CC2500 Status registers
#define TI_CCxxx0_PARTNUM      0x30        // Part number
#define TI_CCxxx0_VERSION      0x31        // Current version number
#define TI_CCxxx0_FREQEST      0x32        // Frequency offset estimate
#define TI_CCxxx0_LQI          0x33        // Demodulator estimate for link quality
#define TI_CCxxx0_RSSI         0x34        // Received signal strength indication
#define TI_CCxxx0_MARCSTATE    0x35        // Control state machine state
#define TI_CCxxx0_WORTIME1     0x36        // High byte of WOR timer
#define TI_CCxxx0_WORTIME0     0x37        // Low byte of WOR timer
#define TI_CCxxx0_PKTSTATUS    0x38        // Current GDOx status and packet status
#define TI_CCxxx0_VCO_VC_DAC   0x39        // Current setting from PLL cal module
#define TI_CCxxx0_TXBYTES      0x3A        // Underflow and # of bytes in TXFIFO
#define TI_CCxxx0_RXBYTES      0x3B        // Overflow and # of bytes in RXFIFO
#define TI_CCxxx0_NUM_RXBYTES  0x7F        // Mask "# of bytes" field in _RXBYTES

// CC2500 Other memory locations
#define TI_CCxxx0_PATABLE      0x3E
#define TI_CCxxx0_TXFIFO       0x3F
#define TI_CCxxx0_RXFIFO       0x3F

// CC2500 Masks for appended status bytes
#define TI_CCxxx0_LQI_RX       0x01        // Position of LQI byte
#define TI_CCxxx0_CRC_OK       0x80        // Mask "CRC_OK" bit within LQI byte

// CC2500 Definitions to support burst/single access:
#define TI_CCxxx0_WRITE_BURST  0x40
#define TI_CCxxx0_READ_SINGLE  0x80
#define TI_CCxxx0_READ_BURST   0xC0


//-------------------------------
// 25LC256 EEPROM defines
//-------------------------------

#define     EEPROM_WREN          0x06       // EEPROM Write Enable Instruction
#define     EEPROM_WRITE         0x02       // EEPROM Write Instruction
#define     EEPROM_READ          0x03       // EEPROM Read Instruction
#define     EEPROM_RSR           0x05       // EEPROM Read Status Register Instruction


//-------------------------------
// General defines
//-------------------------------

#define     TRUE                  1
#define     FALSE                 0

#define     PAYLOAD_SIZE          16

#define     CHANNEL_1             20        // RF Channel for TAG Scan
#define     CHANNEL_2             21        // RF Channel for TAG Read-Write transaction


#define     TEMPERATURE           0x00
#define     BATTERY               0x01

#define     ZERODBM               0xFE      // 0dBm is default Tx Power

#define     TAG_UID_SET           0x3C      //  UID Set Command


#define     TAG_BASIC             0x10
#define     TAG_SENSO             0x20
#define     TAG_LOGGO             0x30


#define     TI_CC_SPI_USART0_PxIN     P1IN      // MSP430 SPI Port
#define     TI_CC_SPI_USART0_SOMI     0x80      // for MSP430F2012 SOMI is P1.7


//-------------------------------
// Global variables
//-------------------------------
unsigned char tx_array [20], rx_array [20];                 // tx and rx data arrays
unsigned char uid [5] = {0xAA,0xBB,0xCC,0xDD,0xEE};         // UID array-default UID, Rx-Address is UID first 5 bytes
char tx_finished, rx_finished;                              // RF interface status variables
char payload_sentreceived = FALSE;                          // RF interface status variables
char stat_CC2500;                                         
signed char  tx_count, rx_count;                            // index counters
unsigned int  i,j;                                          // index counters
unsigned int wait_count;                                    // random wait count
int  battery_voltage;                                       // battery voltage value after ADC
unsigned int wakeup_tick = 1;                               // wakeup counter
unsigned char sr1,sr2,sr3,sr4;                              // shift register values for randomizer
char timeout;
char CC2500_error;
unsigned char rssi;
unsigned int test_count = 0;
unsigned char dummy;

//-------------------------------
// Function Declarations
//-------------------------------
void randomizer (void);
void txmit_id (void);
void write_uid (void);
void read_uid(void);

void powerdown_rf (void);
void por_CC2500 (void);
void write_CC2500_reg (char reg, char data);
void write_CC2500_commandstrobe (char command_strobe);
void burstwr_CC2500_FIFO (void);
void txmit_payload (char channel);
unsigned char read_CC2500_statusreg (unsigned char reg);
void rcv_payload (void);
void init_CC2500_default (void);
void init_CC2500_rx (char channel);

int  read_adc (char temp_or_bat);

 

 

void main(void)
{
  WDTCTL = WDTPW + WDTHOLD;                                 // Stop WDT
  BCSCTL3 = XCAP_2;                                         // 10pF cap selected to provide 10+2//10+2 = 6pF as load cap
  for (j=0; j<10000; j++);                                  // Delay for DCO to stabilize
  BCSCTL1 = CALBC1_8MHZ;                                    // DCO=8MHz, ACLK=32768Hz
  DCOCTL = CALDCO_8MHZ;
  FCTL2 = FWKEY + FSSEL0 + FN4 + FN3;                       // MCLK/(24+1) for Flash Timing Generator
 
// Init Digital I/O ports
  P1OUT = 0x1C;                                             // Set CS2500, CSEEPROM, WREEPROM high
  P1DIR = 0x1C;                                             // Set P1.2, P1.3, P1.4 output
  P1IE |= 0x01;                                             // P1.0 interrupt enabled
  P1IES |= 0x01;                                            // P1.0 = CC2500 GDO-0, Hi-to-low edge asserted when packet received
  P1IFG &= ~0x01;                                           // P1.0 IFG cleared
 

// Init Timer-A0 for LPM3 wakeup
//  TACTL = TASSEL_1 + ID_1 + MC_1;                           // TACLK = ACLK, /2 clk-divide, Up mode to CCR0.
//  TACCR0 = 32768;                                           // Settings for Period = 1 sec
//  TACCTL0 |= CCIE;                                          // Compare-mode interrupt enabled.


// Init USI Module to SPI Mode
  USICTL0 |= USISWRST;                                      // Hold SPI in Reset state
  USICTL0 = USIPE7 + USIPE6 + USIPE5 + USIMST + USIOE;      // Enable SDI,SDO,SCLK, SPI Master Mode, USI output enable
  USICTL1 = USICKPH + USIIE;                                // Clock phase select, USI counter interrupt enable
  USICKCTL = USISSEL1;                                      // SPICLK = SMCLK
  USISRL = 0x00;                                            // Ensure SDO low instead of high
  USICTL0 &= ~USISWRST;                                     // Enable SPI operation
  _EINT();
  
  
  por_CC2500 ();
  init_CC2500_default();
  dummy = read_CC2500_statusreg (TI_CCxxx0_PARTNUM);
  dummy = read_CC2500_statusreg (TI_CCxxx0_RXBYTES);
  write_CC2500_commandstrobe(TI_CCxxx0_SFRX);               // Flush RX buffer


 while (1)
  {
    payload_sentreceived = FALSE;
    init_CC2500_rx (CHANNEL_1);
    do
    {
      LPM0;
    }
    while (!payload_sentreceived);
    rcv_payload ();
    ++test_count;
  }  /*------------End of endless while----------*/
}  /*------------End Main----------*/

 

//-----------------------------------------------------------------------------
// TAG and Reader interface packet handling routines
//-----------------------------------------------------------------------------

void randomizer ()
{
  unsigned char e1,e2,e3,e4,fb,t;
 
  for (j=0; j<8; j++)                                       // turn 8 times for byte value
  {
    e1 = sr1 >> 6;                                          // bit-2
    e2 = sr1 >> 7;                                          // bit-1
    e3 = sr3 >> 2;                                          // bit-22
    e4 = sr4 & 0x01;                                        // bit-32
    fb = e1 ^ e2 ^ e3 ^ e4;                                 // XOR all bits
   
    sr4 = (sr4 >> 1);                                       // shift all sr values right
    t = sr3 << 7;
    sr4 |= t;
   
    sr3 = (sr3 >> 1);
    t = sr2 << 7;
    sr3 |= t;
   
    sr2 = (sr2 >> 1);
    t = sr1 << 7;
    sr2 |= t;
   
    sr1 = (sr1 >> 1);
    sr1 |= (fb << 7);                                       // feed the fb value to 1st bit
  }
}

 

void txmit_id (void)
{
      for (j=0; j<5; j++) tx_array [j] = uid [4-j];
      for (j=0; j<8; j++) tx_array [j+5] = 0xA3;            // dummy data
      tx_array [13] = (char) battery_voltage;               // battery voltage-LSB
      tx_array [14] = (char) (battery_voltage >> 8);        // battery voltage-MSB
      tx_array [15] = TAG_BASIC;                            // First byte describes the TAG type
      txmit_payload (CHANNEL_1);                            // txmit SID packet  
}


void write_uid ()
{
  char *Flash_ptrC;                                         // Segment C pointer

  Flash_ptrC = (char *) 0x1040;                             // Initialize Flash segment C pointer

  FCTL1 = FWKEY + ERASE;                                    // Set Erase bit
  FCTL3 = FWKEY;                                            // Clear Lock bit
 
  *Flash_ptrC = 0;                                          // Dummy write to erase Seg-C
  for (j=0; j<30000; j++);

  FCTL1 = FWKEY + WRT;                                      // Set WRT bit for write operation
  *Flash_ptrC++ = 0x55;                                     // Segment in use mark
  for (j=0; j<5; j++) *Flash_ptrC++ = rx_array [13-j];      // Write UID to Seg-C

  FCTL1 = FWKEY;                                            // Clear WRT bit
  FCTL3 = FWKEY + LOCK;                                     // Set LOCK bit
  read_uid();
}

          
void read_uid(void)                         // Reads UID from Seg-C or Seg-D
{                                           // 1st byte = 0x55 if valid UID is present in the Segment
  char *Flash_ptrC;                         // Segment C pointer

  Flash_ptrC = (char *) 0x1040;             // Initialize Flash segment C pointer
 
  if (*Flash_ptrC++ == 0x55) for (j=0; j<5; j++) uid [j] = *Flash_ptrC++;
 
  sr1 = uid [1];
  sr2 = uid [2];
  sr3 = uid [3];
  sr4 = uid [4];
}

 


//-----------------------------------------------------
// CC2500 interface routines
//-----------------------------------------------------


void powerdown_rf (void)
{
  write_CC2500_commandstrobe (TI_CCxxx0_SPWD);            // powerdown CC2500
}


void por_CC2500 (void)
{
  P1OUT |= 0x04;                                            // Set CS-CC2500 High
  for (j=0; j<100; j++);                                    // ~40us delay
  P1OUT &= ~0x04;                                           // Set CS-CC2500 Low
  for (j=0; j<100; j++);                                    // ~40us delay
  P1OUT |= 0x04;                                            // Set CS-CC2500 High
  for (j=0; j<150; j++);                                    // ~70us delay
  P1OUT &= ~0x04;                                           // Set CS-CC2500 Low
  while (TI_CC_SPI_USART0_PxIN & TI_CC_SPI_USART0_SOMI);    // Wait for CC2500 ready
  tx_finished = 0;
  rx_count = 0;
  tx_count = 0;
  USISRL = TI_CCxxx0_SRES;                                  // Write commandstrobe
  USICNT = 0x08;                                            // Write the no of bits (8) to be txmitted
  do                                                        // SPI Tx Started
  {
  LPM0;
  }
  while (!tx_finished);
  while (TI_CC_SPI_USART0_PxIN & TI_CC_SPI_USART0_SOMI);    // Wait for CC2500 ready
  P1OUT |= 0x04;                                            // Set CS-CC2500 High
}


void write_CC2500_reg (char reg, char data)
// Writes the data to CC2500 register
{
  tx_finished = 0;
  rx_count = 0;
  tx_count = 1;
  tx_array [0] = data;
  P1OUT &= ~0x04;                                           // Set CS2500 Low to start SPI cycle
  while (TI_CC_SPI_USART0_PxIN & TI_CC_SPI_USART0_SOMI);    // Wait for CC2500 ready
  USISRL = reg;                                             // register-wr, no-burst
  USICNT = 0x08;                                            // Write the no of bits (8) to be txmitted
  do                                                        // SPI Tx Started
  {
  LPM0;
  }
  while (!tx_finished);
  P1OUT |= 0x04;                                            // Set CS2500 High to finish SPI cycle
  stat_CC2500 = rx_array [0];                               // CC2500 status is read after first byte wr
}


void write_CC2500_commandstrobe (char command_strobe)
// Writes the command strobe to CC2500
{
  tx_finished = 0;
  rx_count = 0;
  tx_count = 0;
  P1OUT &= ~0x04;                                           // Set CS2500 Low to start SPI cycle
  while (TI_CC_SPI_USART0_PxIN & TI_CC_SPI_USART0_SOMI);    // Wait for CC2500 ready
  USISRL = command_strobe;                                  // Write commandstrobe
  USICNT = 0x08;                                            // Write the no of bits (8) to be txmitted
  do                                                        // SPI Tx Started
  {
  LPM0;
  }
  while (!tx_finished);
  P1OUT |= 0x04;                                            // Set CS2500 High to finish SPI cycle
  stat_CC2500 = rx_array [0];                               // CC2500 status is read after commandstrobe wr
}

 

unsigned char read_CC2500_statusreg (unsigned char reg)
// Reads the data from CC2500 register
{
  tx_finished = 0;
  rx_count = 0;
  tx_count = 1;
  tx_array [0] = 0x55;                                      // dummy data
  P1OUT &= ~0x04;                                           // Set CS2500 Low to start SPI cycle
  while (TI_CC_SPI_USART0_PxIN & TI_CC_SPI_USART0_SOMI);    // Wait for CC2500 ready
  USISRL = (reg | TI_CCxxx0_READ_BURST);                   // register-rd, no-burst
  USICNT = 0x08;                                            // Write the no of bits (8) to be txmitted
  do                                                        // SPI Tx Started
  {
  LPM0;
  }
  while (!tx_finished);
  P1OUT |= 0x04;                                            // Set CS2500 High to finish SPI cycle
  stat_CC2500 = rx_array [0];                               
  return (rx_array[1]);                                     // CC2500 status-reg is read as second byte
}

 


void burstwr_CC2500_FIFO (void)
// writes PAYLOAD_SIZE byte tx-data to TX FIFO
// assumes data is preloaded in tx_array
// PAYLOAD_SIZE must be > 1
{
  tx_finished = 0;
  rx_count = 0;
  tx_count = PAYLOAD_SIZE;
  P1OUT &= ~0x04;                                           // Set CS2500 Low to start SPI cycle
  while (TI_CC_SPI_USART0_PxIN & TI_CC_SPI_USART0_SOMI);    // Wait for CC2500 ready
  USISRL = (TI_CCxxx0_TXFIFO | TI_CCxxx0_WRITE_BURST);      // TX-FIFO-wr, burst-mode
  USICNT = 0x08;                                            // Write the no of bits (8) to be txmitted
  do                                                        // SPI Tx Started
  {
  LPM0;
  }
  while (!tx_finished);
  P1OUT |= 0x04;                                            // Set CS2500 High to finish SPI cycle
  stat_CC2500 = rx_array [0];                               // CC2500 status is read after first byte wr
}

 

void txmit_payload (char channel)
{
//  while (read_CC2500_statusreg (TI_CCxxx0_TXBYTES) < PAYLOAD_SIZE); // wait for TX FIFO empty
//  write_CC2500_reg (TI_CCxxx0_CHANNR, channel);             // set Channel number
  burstwr_CC2500_FIFO ();                                   // fill the TX FIFO
  write_CC2500_commandstrobe (TI_CCxxx0_STX);               // start TX
//  powerdown_rf ();
}

 

void rcv_payload (void)
// wait for RX, read CC2500 PAYLOAD,
// returns in rx_array
// read RSSI
{
unsigned char no_bytes_rcvd;
  for (j=0; j<1500; j++);
  CC2500_error = FALSE;
//  write_CC2500_commandstrobe(TI_CCxxx0_SFRX);               // Flush RX buffer

  no_bytes_rcvd = read_CC2500_statusreg (TI_CCxxx0_RXBYTES);// read no of bytes rcvd
//  no_bytes_rcvd = 0x10;
//  if (no_bytes_rcvd > PAYLOAD_SIZE)
//  {
//    write_CC2500_commandstrobe(TI_CCxxx0_SFRX);             // more bytes are read than expected, flush RX Buffer
//    CC2500_error = TRUE;
//  }
//  else
//  {     
  tx_finished = FALSE;
  rx_count = 0;
  tx_count = no_bytes_rcvd;

  for (j=0; j<no_bytes_rcvd; j++) tx_array [j] = 0x55;      // dummy data
  P1OUT &= ~0x04;                                           // Set CS2500 Low to start SPI cycle
  while (TI_CC_SPI_USART0_PxIN & TI_CC_SPI_USART0_SOMI);    // Wait for CC2500 ready
  USISRL = (TI_CCxxx0_RXFIFO | TI_CCxxx0_READ_BURST);       // RX-FIFO-rd, burst-mode                                    // register-rd, no-burst
  USICNT = 0x08;                                            // Write the no of bits (8) to be txmitted
  do                                                        // SPI Tx Started
  {
  LPM0;
  }
  while (!tx_finished);
  P1OUT |= 0x04;                                            // Set CS2500 High to finish SPI cycle
  stat_CC2500 = rx_array [0];                               // CC2500 status-reg is read as second byte  
 
  rssi = read_CC2500_statusreg (TI_CCxxx0_RSSI);            // read RSSI value
//  }
}

 

void init_CC2500_rx (char channel)
{
//  write_CC2500_reg (TI_CCxxx0_CHANNR, channel);             // set Channel number
  write_CC2500_commandstrobe (TI_CCxxx0_SRX);               // Start RX
}


void init_CC2500_default (void)
// Product = CC2500
// Crystal accuracy = 40 ppm
// X-tal frequency = 26 MHz
// RF output power = 0 dBm
// RX filterbandwidth = 540.000000 kHz
// Deviation = 0.000000
// Return state:  Return to RX state upon leaving either TX or RX
// Datarate = 250.000000 kbps
// Modulation = (7) MSK
// Manchester enable = (0) Manchester disabled
// RF Frequency = 2433.000000 MHz
// Channel spacing = 199.950000 kHz
// Channel number = 0
// Optimization = Sensitivity
// Sync mode = (3) 30/32 sync word bits detected
// Format of RX/TX data = (0) Normal mode, use FIFOs for RX and TX
// CRC operation = (1) CRC calculation in TX and CRC check in RX enabled
// Forward Error Correction = (0) FEC disabled
// Length configuration = (1) Fixed length packets
// Packetlength = 16
// Preamble count = (2)  4 bytes
// Append status = 1
// Address check = (0) No address check
// FIFO autoflush = 0
// Device address = 0
// GDO0 signal selection = (0X47) Asserts when packet received, and de-asserts when first byte is read from FIFO
// GDO2 signal selection = (0X29) CHPRDY
{
    // Write register settings
    write_CC2500_reg (TI_CCxxx0_IOCFG2,   0x29); // GDO-2 will be used as default to signal CHPRDY (chip ready) 
    write_CC2500_reg (TI_CCxxx0_IOCFG0,   0x06); // GDO-0 asserted-low when packet received
    write_CC2500_reg (TI_CCxxx0_PKTLEN,   0x10); // Packet length is 16 bytes
    write_CC2500_reg (TI_CCxxx0_PKTCTRL1, 0x00); // Packet automation control.
    write_CC2500_reg (TI_CCxxx0_PKTCTRL0, 0x84); // Packet automation control.
    write_CC2500_reg (TI_CCxxx0_ADDR,     0x01); // Device address.
    write_CC2500_reg (TI_CCxxx0_CHANNR,   0x05); // Channel number.
    write_CC2500_reg (TI_CCxxx0_FSCTRL1,  0x07); // Freq synthesizer control.
    write_CC2500_reg (TI_CCxxx0_FSCTRL0,  0x00); // Freq synthesizer control.
    write_CC2500_reg (TI_CCxxx0_FREQ2,    0x5D); // Freq control word, high byte
    write_CC2500_reg (TI_CCxxx0_FREQ1,    0x93); // Freq control word, mid byte.
    write_CC2500_reg (TI_CCxxx0_FREQ0,    0xB1); // Freq control word, low byte.
    write_CC2500_reg (TI_CCxxx0_MDMCFG4,  0x2D); // Modem configuration.
    write_CC2500_reg (TI_CCxxx0_MDMCFG3,  0x3B); // Modem configuration.
    write_CC2500_reg (TI_CCxxx0_MDMCFG2,  0x73); // Modem configuration.
    write_CC2500_reg (TI_CCxxx0_MDMCFG1,  0x22); // Modem configuration.
    write_CC2500_reg (TI_CCxxx0_MDMCFG0,  0xF8); // Modem configuration.
    write_CC2500_reg (TI_CCxxx0_DEVIATN,  0x00); // Modem dev (when FSK mod en)
    write_CC2500_reg (TI_CCxxx0_MCSM1 ,   0x00); // MainRadio Cntrl State Machine
    write_CC2500_reg (TI_CCxxx0_MCSM0 ,   0x18); // MainRadio Cntrl State Machine
    write_CC2500_reg (TI_CCxxx0_FOCCFG,   0x1D); // Freq Offset Compens. Config
    write_CC2500_reg (TI_CCxxx0_BSCFG,    0x1C); // Bit synchronization config.
    write_CC2500_reg (TI_CCxxx0_AGCCTRL2, 0xC7); // AGC control.
    write_CC2500_reg (TI_CCxxx0_AGCCTRL1, 0x00); // AGC control.
    write_CC2500_reg (TI_CCxxx0_AGCCTRL0, 0xB2); // AGC control.
    write_CC2500_reg (TI_CCxxx0_FREND1,   0xB6); // Front end RX configuration.
    write_CC2500_reg (TI_CCxxx0_FREND0,   0x10); // Front end TX configuration.
    write_CC2500_reg (TI_CCxxx0_FSCAL3,   0xEA); // Frequency synthesizer cal.
    write_CC2500_reg (TI_CCxxx0_FSCAL2,   0x0A); // Frequency synthesizer cal.
    write_CC2500_reg (TI_CCxxx0_FSCAL1,   0x00); // Frequency synthesizer cal.
    write_CC2500_reg (TI_CCxxx0_FSCAL0,   0x11); // Frequency synthesizer cal.
    write_CC2500_reg (TI_CCxxx0_FSTEST,   0x59); // Frequency synthesizer cal.
    write_CC2500_reg (TI_CCxxx0_TEST2,    0x88); // Various test settings.
    write_CC2500_reg (TI_CCxxx0_TEST1,    0x31); // Various test settings.
    write_CC2500_reg (TI_CCxxx0_TEST0,    0x0B); // Various test settings.
   
    write_CC2500_reg (TI_CCxxx0_PATABLE,  ZERODBM); // Set TX Power Level to 0 dBm
                                                 // always txmit at max power level (0dBm)
}

 


//-----------------------------------------------------------------------------
// A/D Converter Interface Routines
//-----------------------------------------------------------------------------

int read_adc (char temp_or_bat)
{
  int conversion;
  if (temp_or_bat == TEMPERATURE) ADC10CTL1 = ADC10DIV_3 + INCH_10 + SHS_0 + CONSEQ_0;
    else ADC10CTL1 = ADC10DIV_3 + INCH_11 + SHS_0 + CONSEQ_0;
  ADC10CTL0 = SREF_1 + ADC10SHT_3 + ADC10SR + REFON + ADC10ON;       
                                                            // VR+=VREF+ and VR-=VSS, 64xADC10CLKs SH time
                                                            // Sample Rate=50ksps, Ref is on and=1.5V
  for (j=1; j<80; j++);                                     // > 30uS delay to settle VRef
  ADC10CTL0 |= ENC + ADC10SC;                               // ADC10 Enable conversion and start conversion
  while (!(ADC10IFG & ADC10CTL0));                          // Wait for conversion to finish
  conversion = ADC10MEM;
  ADC10CTL0 &= ~(ADC10IFG + ENC);                           // Clear ENC and IFlag
  ADC10CTL0 &= ~(ADC10ON + REFON);                          // Shutdown ADC
  return (conversion);
}

 


//-----------------------------------------------------------------------------
// Interrupt Service Routines
//-----------------------------------------------------------------------------


#pragma vector=USI_VECTOR
__interrupt void USI_txrx (void)
{
  _BIC_SR_IRQ(LPM0_bits);                                   // Clear LPM0 bits from 0(SR)
  tx_count--;
  if (tx_count < 0)
  {
    USICTL1 &= ~0x01;                                       // Clear USIIFG
    tx_finished = 0x01;
    rx_array [rx_count] = USISRL;
    ++rx_count;
  }
  else
  {
    rx_array [rx_count] = USISRL;
    USISRL = tx_array [tx_count];
    USICNT = 0x08;                                          // Write the no of bits (8) to be txmitted
    ++rx_count;
  }
}


// Port 1 interrupt service routine for CC2500 INT
#pragma vector=PORT1_VECTOR
__interrupt void Port_1(void)
{
  _BIC_SR_IRQ(LPM0_bits);                                   // Clear LPM0 bits from 0(SR)
  P1IFG &= ~0x01;                                           // P1.0 IFG cleared
  payload_sentreceived = TRUE;                              // CC2500 GDO-0 INT meaning RX event occured
}


#pragma vector=TIMERA0_VECTOR
__interrupt void ta0_isr(void)
{
  LPM3_EXIT;                                                // Exit LPM3 on return
  timeout = TRUE;
}

 

 

2 Replies

  • Hi Samarth,

    I only had a very quick look but I would try the following two things

    1) Make sure you also set the P1SEL correctly

    2) I don't see you enablling interrupts with the following command

      __bis_SR_register(GIE);       // enable interrupts

    Also give that a try.

    I do hope the above helps. 

    Cheers,
    Yoda

     

  • In reply to Lisa TI:

    Hey thanks Yoda for your help. I am very grateful to you. I have implemented the required changes. However, I was trying to figure the problem with receiver program, I realized i should check whether the transmitter is transmitting any RF packets. I found out that it was NOT transmitting any packets. The transmitter is only transmitting the tag data when it is in debug mode. I can monitor the operation of the microcontroller in debug mode, when the FLASH PROGRAMMER (MSP-FETU430IF) is connected to the board in Spy-Bi Wire mode. But once i remove the flash programmer, it does not transfer any packet. I checked the signals using a oscilloscope and i found that there was no signal on the GDO-0 PIN.

    I followed the following procedure:
    1) I changed the project settings from 'debug' to 'release'. The release
    mode creates a .txt file containing instructions that have to be written
    to the flash memory of the MSP430F2012. the size of the .txt file must be
    withing the 2kb flash range of the device. In my case the file equals to
    around 1.641kb.

    2) the IAR workbench is not able to download this file into flash memory,
    hence i used a tool called FET-PRO430 (produced by Elprotronic). I
    managed to write to the flash memory but the same problem continues.

    3) I created a manual interrupt on the GDO-0 pin to see if the program is
    interrupting on the signals to the GDO-0 pin.

    In conclusion i can say that the transmitter is transmitting the packets
    in debug mode. Once i break connections with the flash programmer tool ,
    there are no signals on the GDO-O pin. The receiver program is working.

     

    Any help regarding this matter will be appreciated!!

     

    Thanks

    Samarth