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How to get the UART working in POWER_SAVING mode?

Other Parts Discussed in Thread: CC2540, CC2541

I use the 1.3.0 stack, UART in ISR mode. Now if I comment the POWER_SAVING in preprocessor, it is OK using 9600 baud without any problem. But if I add the power_saving, data get corrupted each time when IOS send data or PC send data. So how to get power_saving work. Or is it impossible to get it work properly when POWER_SAVING is on?

  • as far as i know you can't use the UART with powersaving.

    my digging produced the following factoids when i had the same problem:

    • UART is clocked by 32Mhz OSC only
    • depending on powermode 32Mhz is disabled with only 32kHz remaining
    • you can't advise the stack WHICH powermodes to use

    my current solution wakes up the cc2540 with a GPIO-IRQ which then disables powersaving to be able to receive data.

    Edit 1: and don't forget to disable ClockDivOnHalt by calling HCI_EXT_ClkDivOnHaltCmd(HCI_EXT_DISABLE_CLK_DIVIDE_ON_HALT); or you will have a very bad time :)

  • Thanks for your suggestion. So I need to use the P0.X to sync with UART.

     

    Chris

  • Andre S said:

    as far as i know you can't use the UART with powersaving.

    That's what I thought, too, and I'm working on implementing SPI.  But reading closer through the code, it seems that the chip select/rts pins can use double duty - as signal and as GPIO wake-ups.  I haven't got back to test the wakeup with the UART, as I expect to have slightly better control through SPI.

    But the idea is that you need to wake up the CC2541, wait 700 us, then you can talk to it.  At least this is what I'm seeing with SPI.

  • Just to clarify, when stating that you are "waking up the CC2541, waiting 700us, then talk to it."

    Are you directly using the CS as the wake up?

    Right now I have code that calls the GPIO Interrupt when CS goes low. I'm not sure what to do within this code though?

    Do I still jump to my SPI ISR from within this ISR? Or do I simply call this function to wake up the device, clear the GPIO Interrupt flag, and then wait for the UART ISR to be called when being talked to. (Assuming 700us from CS going low to data being written).

    Therefore this is assuming everything is handled by the OSAL, and as long as too much time between CS going low and data being written the system will be ready for UART interrupts?

    Thanks for any clarification on this.