This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CC2640 SCLK_LF Clock Fault Handling

I have a few question relating to the clock loss operation on SCLK_LF.

1) SCLK_LF is set to use 32.768kHz Crystal, Crystal fails.  What source is applied to SCLK_LF? 

From the documentation, I would say that nothing is automatically applied and the system would halt.

If CTL0.CLK_LOSS_EN=1 and RESETCTL.CLK_LOSS_EN=1, the system would generate a reset.

Check AUX_DDIO_OSC:AON_SYSCTL:RESETCTL.RESET_SRC to see if clock loss was the cause of the RESET.  

Check AUX_DDIO_OSC:STAT0.SCLK_LF_LOSS to see if SCLK_LF_LOSS caused the reset.

At this point, another SCLK_LF option can be selected as follows:

SCLK_LF is controlled CTL0.SCLK_LF_SRC_SEL as follows:

0h = Low frequency clock derived from High Frequency RCOSC

1h = Low frequency clock derived from High Frequency XOSC

2h = Low frequency RCOSC

3h = Low frequency XOSC

Is this an accurate assessment? Is there a code example showing this handling? 

2) How is the Watchdog clock source handled when the SCLK_LF clock source fails?

Would this be applied in the same manner as Question #1?

3) What is applied to SCLK_LF if CTL0.SCLK_LF_SRC_SEL=3h and there is a fault on the Low Frequency XOSC? 

Does it remain at the default Low frequency clock derived from High Frequency RCOSC?  If so, what happens to the operation if the device attempts to enter Standby.  Will the High Frequency RCOSC shut off and block wakeup from Standby?

Thanks,

Robb

 

  • Hi Robb,

    I am looking into this. Some of our core experts are out on vacation, so I will need a couple of days to figure this out.

    Best regards,
    Fredrik
  • Hi Fredrik,

    Thank you for digging into this.  I am going to try some experiments myself.

    Cheers,

    Robb

  • Hi Robb,

    I have not been able to get firm answers to your questions yet due to people being out on vacation, but here are my assumptions at least:

    1) I think you are right. Nothing will happen automatically, and the code should switch to RCOSC_LF if the XOSC_LF fails and causes a reset.
    2) Same as above
    3) Is the question "what happens if we switch to XOSC_LF and it does not start up"?

    Best regards,
    Fredrik
  • And one more thing: At start-up, they must wait until after they have switched to XOSC_LF before turning on the clock loss detector.
  • Hi Fredrik,

    I have been playing with the SimpleBLEPeripheral example code, and I have added the following to the main() loop before applying the BIOS_start().

    =========================================

    currentStat0 = (HWREG( AUX_DDI0_OSC_BASE + DDI_0_OSC_O_STAT0 ) & DDI_0_OSC_STAT0_SCLK_LF_LOSS);

    currentResetCtl = (HWREG( AON_SYSCTL_BASE + AON_SYSCTL_O_RESETCTL ) &    

                                 AON_SYSCTL_RESETCTL_RESET_SRC_M);

    switch(currentResetCtl) {

       case AON_SYSCTL_RESETCTL_RESET_SRC_CLK_LOSS:    

           if (currentStat0  == DDI_0_OSC_STAT0_SCLK_LF_LOSS) {  // If SCLK_LF_LOSS occurs, switch to RCOSC_LF

               GPIOPinWrite(GPIO_PIN_6, 1);        

               OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_RCOSC_LF );

               while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != OSC_RCOSC_LF ) {

                   // Wait until switched

               }              

           }    

           else {    // Then SCLK_HF_LOSS occurred, start OSC_XOSC_LF (External 32.768kHz Crystal)

               GPIOPinWrite(GPIO_PIN_7, 1);        

               OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF );

               while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != OSC_XOSC_LF ) {        

                   // Wait until switched

               }              

           }    

           break;

       case AON_SYSCTL_RESETCTL_RESET_SRC_VDDS_LOSS: // Did VDDS_LOSS cause reset?

           GPIOPinWrite(GPIO_PIN_25, 1);    

           OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF );

           while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != OSC_XOSC_LF ) {

               // Wait until switched

           }                

           break;

       case AON_SYSCTL_RESETCTL_RESET_SRC_SYSRESET:            

           GPIOPinWrite(GPIO_PIN_27, 1);  

           OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF );

           while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != OSC_XOSC_LF ) {

               // Wait until switched

           }                  

           break;            

       default:     // Default, start OSC_XOSC_LF (External 32.768kHz Crystal)

           OSCClockSourceSet( OSC_SRC_CLK_LF, OSC_XOSC_LF );

           while( OSCClockSourceGet( OSC_SRC_CLK_LF ) != OSC_XOSC_LF ) {          

               // Wait until switched

           }            

           break;

    }

    // Turn ON Clock Loss Detection.

    HWREG( AUX_DDI0_OSC_BASE + DDI_O_SET + DDI_0_OSC_O_CTL0 ) = DDI_0_OSC_CTL0_CLK_LOSS_EN;

    =========================================

    This is to better understand the RESETs.  

    On Powerup or EM Reset, I run through default and set the OSC_SRC_CLK_LF to use the external 32.768kHz Crystal.

    When I short X32K_Q2 off the Crystal to GND, it generates an SCLK_LOSS Reset.  At this point, I check for SCLK_LF_LOSS in STAT0.  If this is set, then I change SCLK_LF to OSC_RCOSC_LF.

    At this point, I run SCLK_LF from OSC_RCOSC_LF (Advertise and Connect Possible).

    Now, when I short X32K_Q2 off the Crystal to GND, it still generates an SCLK_LOSS Reset.

    Am I doing something wrong with the switch?  I would not have expected the SCLK_LOSS to occur if I am running off of the internal RCOSC_LF.

    I do have a follow-up question about the BOD operation, but I will start this as a separate post.

    Thanks,

    Robb

  • Hi, Robb:
    My customer has 32K external osc failure issue, the failure protect code as your showed seems could help solve the problem.
    So have you already dig out the bug and make it work as you expected? Thanks!

    Vivian