I have a few question relating to the clock loss operation on SCLK_LF.
1) SCLK_LF is set to use 32.768kHz Crystal, Crystal fails. What source is applied to SCLK_LF?
From the documentation, I would say that nothing is automatically applied and the system would halt.
If CTL0.CLK_LOSS_EN=1 and RESETCTL.CLK_LOSS_EN=1, the system would generate a reset.
Check AUX_DDIO_OSC:AON_SYSCTL:RESETCTL.RESET_SRC to see if clock loss was the cause of the RESET.
Check AUX_DDIO_OSC:STAT0.SCLK_LF_LOSS to see if SCLK_LF_LOSS caused the reset.
At this point, another SCLK_LF option can be selected as follows:
SCLK_LF is controlled CTL0.SCLK_LF_SRC_SEL as follows:
0h = Low frequency clock derived from High Frequency RCOSC
1h = Low frequency clock derived from High Frequency XOSC
2h = Low frequency RCOSC
3h = Low frequency XOSC
Is this an accurate assessment? Is there a code example showing this handling?
2) How is the Watchdog clock source handled when the SCLK_LF clock source fails?
Would this be applied in the same manner as Question #1?
3) What is applied to SCLK_LF if CTL0.SCLK_LF_SRC_SEL=3h and there is a fault on the Low Frequency XOSC?
Does it remain at the default Low frequency clock derived from High Frequency RCOSC? If so, what happens to the operation if the device attempts to enter Standby. Will the High Frequency RCOSC shut off and block wakeup from Standby?
Thanks,
Robb