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MSP430F5483A + CC2564B problem stack init failed -4

Other Parts Discussed in Thread: BT-MSPAUDSINK, MSP430F5438A, MSP430F5438, MSP430F5229

Hello

I am currently working on a project that uses the MSP430F5438A in combination with the CC2564B bluetooth chip. As a proof of concept we have worked with the BT-MSPAUDSINK board that did the job very nice.

Now we have designed our own board for the project using an MSP430F5438A. But now we are having a hard time to get the bluetopia code to run on our board. We always get the response of -4 which means that there is a problem with the communication. We have tried for several days and checked hardware over and over again. But the reply is always -4. 

We are not sure if it is a hardware problem or a software problem.

We have used the pinout that was used in the example software like this:

/*****< HRDWCFG.h >************************************************************/
/*      Copyright 2010 - 2014 Stonestreet One.                                */
/*      All Rights Reserved.                                                  */
/*                                                                            */
/*  HRDWCFG - Hardware Configuration header for MSP430 5438 Experimentor      */
/*            Board.                                                          */
/*                                                                            */
/*  Author:  Tim Cook                                                         */
/*                                                                            */
/*** MODIFICATION HISTORY *****************************************************/
/*                                                                            */
/*   mm/dd/yy  F. Lastname    Description of Modification                     */
/*   --------  -----------    ------------------------------------------------*/
/*   08/31/10  Tim Cook       Initial creation.                               */
/******************************************************************************/
#ifndef _HRDWCFG_H_
#define _HRDWCFG_H_
#include <msp430.h>        /* Compiler specific Chip header.                  */
#include "MSP430Utils.h"   /* MSP430 defines and Processor Specific Utilities */

   /* The following typedef represents all of the allowable clock speeds   */
   /* that may be specified in the BT_CPU_FREQ macro.                      */
typedef enum
{
   cf8MHZ_t,
   cf16MHZ_t,
   cf20MHZ_t,
   cf25MHZ_t
} Cpu_Frequency_t;

/******************************************************************************/
/** The following defines control the UART module used for debug logs.       **/
/******************************************************************************/

   /* The DEBUG UART port base.  Should be set to the address of the    */
   /* UCA1.                                                             */
#define BT_DEBUG_UART_BASE             ((unsigned char *)&UCA1CTLW0)

   /* The DEBUG UART Port Interrupt Vector Number.  Used when enable    */
   /* reception of data on the DEBUG UART port.                         */
#define BT_DEBUG_UART_IV               (USCI_A1_VECTOR)

   /* The Bluetooth UART Interrupt Vector Register.                     */
#define BT_DEBUG_UART_IVR              (UCA1IV)

   /* Maximum numbered of buffered characters on the DEBUG UART         */
   /* receiver.                                                         */
#define BT_DEBUG_UART_RX_BUFFER_SIZE   64

   /* Maximum numbered of buffered characters on the DEBUG UART         */
   /* transmitter.                                                      */
   /* * NOTE * If this value is 0 then this will generate to a Blocking */
   /*          Write.                                                   */
#define BT_DEBUG_UART_TX_BUFFER_SIZE   (3*80)

   /* The DEBUG UART I/O Pin Base.  Should be set to the address of the */
   /* Input register of the I/O Port where the desired UART's Tx/Rx pins*/
   /* are located.  For UCA1 this is P5IN.                              */
#define BT_DEBUG_UART_PIN_BASE         (&P5IN)

   /* The DEBUG UART's Tx Pin Mask.  This should be set to BITx where x */
   /* is the pin on the BT_DEBUG_UART_PIN_BASE port.  For UCA1 Tx is on */
   /* Pin 6 on the MSP430.                                              */
#define BT_DEBUG_UART_PIN_TX_MASK      (BIT6)

   /* The DEBUG UART's Rx Pin Mask.  This should be set to BITx where x */
   /* is the pin on the BT_DEBUG_UART_PIN_BASE port.  For UCA1 Rx is on */
   /* Pin 7 on the MSP430.                                              */
#define BT_DEBUG_UART_PIN_RX_MASK      (BIT7)

   /* The DEBUG UART Baudrate, must be in range supported by chip.      */
#define BT_DEBUG_UART_BAUDRATE         9600L

/******************************************************************************/
/** The following defines control the Bluetooth Slow Clock Line.             **/
/******************************************************************************/

   /* The following is the base address of the GPIO Port where the BT   */
   /* Slow Clock line is located.                                       */
#define BT_SLOW_CLOCK_PORT_BASE        ((unsigned char *)&P11IN)

   /* The following is the pin number on BT_SLOW_CLOCK_PORT_BASE which  */
   /* for which the controller's slow clock line is located.            */
#define BT_SLOW_CLOCK_PORT_PIN         (BIT0)

/******************************************************************************/
/** The following defines control the Bluetooth HCI UART Reset Line.         **/
/******************************************************************************/

   /* The following is the base address of the GPIO Port where the BT   */
   /* controlller's reset line is located.  (Default if Port 8)         */
#define BT_DEVICE_RESET_PORT_BASE      ((unsigned char *)&P8IN)

   /* The following is the pin number on BT_DEVICE_RESET_PORT which for */
   /* which the controller's reset line is located.                     */
#define BT_DEVICE_RESET_PORT_PIN       (BIT2)

/******************************************************************************/
/** The following defines control the Bluetooth HCI UART RTS/CTS Lines.      **/
/******************************************************************************/

   /* The base address of the Processor Port on which the RTS Pin is    */
   /* located.  (Default=0x200 is address of P1IN).                     */
#define BT_UART_FLOW_RTS_PIN_BASE      ((unsigned char *)&P1IN)

   /* The base address of the Processor Port on which the CTS Pin is    */
   /* located.  (Default=0x200 is address of P1IN).                     */
#define BT_UART_FLOW_CTS_PIN_BASE      ((unsigned char *)&P1IN)

   /* The following is the interrupt vector offset of the RTS/CTS Port. */
#define BT_UART_CTS_IV                 (PORT1_VECTOR)

   /* The following is the UART RTS/CTS Interrupt Vector Register.      */
#define BT_UART_CTS_IVR                (P1IV)

   /* The Bluetooth RTS Output Port Pin Number.                         */
#define BT_UART_RTS_PIN                (BIT4)

   /* The Bluetooth CTS Input Port Pin Number.                          */
#define BT_UART_CTS_PIN                (BIT3)

   /* The Bluetooth CTS Interrupt Number.  This should be in the form   */
   /* PXIV_PXIFGY where X is the Port Number (1 in this case) and Y is  */
   /* the Pin Number on the corresponding port (3 in this case).        */
#define BT_UART_CTS_INT_NUM            (P1IV_P1IFG3)

/******************************************************************************/
/** The following group of defines control the UART module used to talk to   **/
/** the Bluetooth Controller chip.                                           **/
/******************************************************************************/

   /* The Base Address of the used UART Module.  On the MSP430x5xx      */
   /* family this is set to the address of the Module's Control Word 0  */
   /* Register.  (All other registers accessed are accessed based on    */
   /* their offset from this Address Base).                             */
#define BT_UART_MODULE_BASE            ((unsigned char *)&UCA2CTLW0)

   /* The Bluetooth UART Interrupt Vector Offset.                       */
#define BT_UART_IV                     (USCI_A2_VECTOR)

   /* The Bluetooth UART Interrupt Vector Register.                     */
#define BT_UART_IVR                    (UCA2IV)

   /* The following is the Base Address of the UART Module's Tx/Rx pin's*/
   /* Port base.  This will be used to configure the Module's Tx/Rx to  */
   /* be used as peripheral pins.                                       */
#define BT_UART_PIN_PORT_BASE          ((unsigned char *)&P9IN)

   /* The UART Module's Tx Pin Mask.                                    */
#define BT_UART_PIN_TX                 (BIT4)

   /* The UART Module's Rx Pin Mask.                                    */
#define BT_UART_PIN_RX                 (BIT5)

/******************************************************************************/
/** The following control the frequency of the processor.                    **/
/******************************************************************************/

   /* The following define controls the speed that the system is        */
   /* configured to run at.                                             */
#define BT_CPU_FREQ                    (cf25MHZ_t)

/******************************************************************************/
/** The following define the Tick Rate for the Bluetopia NoOS Stack.         **/
/******************************************************************************/
#define MSP430_TICK_RATE_HZ            ((unsigned int)1000)
#define MSP430_TICK_RATE_MS            ((unsigned int)1000 / MSP430_TICK_RATE_HZ)

/*************************NON CONFIGURABLE SECTION*****************************/
/*************************NON CONFIGURABLE SECTION*****************************/
/*************************NON CONFIGURABLE SECTION*****************************/
/**                                                                          **/
/** The following sections consist of MACROs that exist to aid in            **/
/** configuring the Bluetooth Chip that should never need to be changed      **/
/** however for completeness they are included in this file.                 **/
/**                                                                          **/
/*************************NON CONFIGURABLE SECTION*****************************/
/*************************NON CONFIGURABLE SECTION*****************************/
/*************************NON CONFIGURABLE SECTION*****************************/

   /* The following MACRO is used to configure the Slow Clock Line.     */
#define BT_CONFIG_SLOW_CLOCK()         GPIOPinTypePeripheralOutput(BT_SLOW_CLOCK_PORT_BASE, BT_SLOW_CLOCK_PORT_PIN)

   /* The following macro is used to configure the Reset line.          */
#define BT_CONFIG_RESET()              GPIOPinTypeReset(BT_DEVICE_RESET_PORT_BASE, BT_DEVICE_RESET_PORT_PIN)

   /* The following is used to Reset the Bluetooth Controller.          */
#define BT_DEVICE_RESET()              HWREG8((BT_DEVICE_RESET_PORT_BASE) + MSP430F5438_GPIO_OUTPUT_OFFSET) &= (~(BT_DEVICE_RESET_PORT_PIN))

   /* The following is used to bring the Bluetooth Controller out of    */
   /* reset.                                                            */
#define BT_DEVICE_UNRESET()            HWREG8((BT_DEVICE_RESET_PORT_BASE) + MSP430F5438_GPIO_OUTPUT_OFFSET) |= (BT_DEVICE_RESET_PORT_PIN)

   /* The following macros are used to configure the RTS/CTS Flow       */
   /* Control Pins for Hardware Flow Control Emulation.                 */
#define BT_CONFIG_RTS_PIN()            GPIOPinTypeRtsFlow(BT_UART_FLOW_RTS_PIN_BASE, BT_UART_RTS_PIN)
#define BT_CONFIG_CTS_PIN()            GPIOPinTypeCtsFlow(BT_UART_FLOW_CTS_PIN_BASE, BT_UART_CTS_PIN)

   /* The following is used to Disable Flow Control with RTS.           */
#define BT_DISABLE_FLOW()              HWREG8((BT_UART_FLOW_RTS_PIN_BASE) + MSP430F5438_GPIO_OUTPUT_OFFSET) |= (BT_UART_RTS_PIN)

   /* The following is used to Re-enable Flow Control with RTS.         */
#define BT_ENABLE_FLOW()               HWREG8((BT_UART_FLOW_RTS_PIN_BASE) + MSP430F5438_GPIO_OUTPUT_OFFSET) &= (~(BT_UART_RTS_PIN))

   /* The following macro is used to make CTS Interrupt Negative Edge   */
   /* Active.                                                           */
#define BT_CTS_INT_NEG_EDGE()          GPIOIntNegEdge((BT_UART_FLOW_CTS_PIN_BASE), (BT_UART_CTS_PIN))

   /* The following Macro returns Non-Zero if CTS Interrupts are        */
   /* currently Negative Edge Active.                                   */
#define BT_CTS_INT_IS_NEG_EDGE()       GPIOIntEdgeIsNeg((BT_UART_FLOW_CTS_PIN_BASE), (BT_UART_CTS_PIN))

   /* The following macro is used to make CTS Interrupt Positive Edge   */
   /* Active.                                                           */
#define BT_CTS_INT_POS_EDGE()          GPIOIntPosEdge((BT_UART_FLOW_CTS_PIN_BASE), (BT_UART_CTS_PIN))

   /* The following macro is used to read the CTS Pin.                  */
#define BT_CTS_READ()                  (GPIORead(BT_UART_FLOW_CTS_PIN_BASE) & (BT_UART_CTS_PIN))

   /* The following macro is used to configure the UART Module's Pins   */
   /* for use by the module.  (Rather than GPIO).                       */
#define BT_CONFIG_UART_PINS()          GPIOPinTypeUART(BT_UART_PIN_PORT_BASE, BT_UART_PIN_TX,BT_UART_PIN_RX)

#endif

Furthermore we have two pins to control the level shifter between the mcu and the CC2564B. Those are the 1V8 enable and Level_shift_enab lines. The hardware can be viewed in the next 2 links:

5025.Main board2.pdf

6327.bluetooth.pdf

We would be very glad to get some insights of some more experienced people who have worked with the bluetopia stack before. 

My sincerly.

  • Hi,

    As you are using the MSP4305438A, you dont have to make any changes in the software. 

    Make sure you follow the first three step from http://processors.wiki.ti.com/index.php/CC256x_Testing_Guide

  • Hello

    We have not really changed anything in the code due to the pinning. 

    We are aware about the power up sequence but this sequence is never replied with a falling edge on the rts line.

    We do the following power up for a test:

    - enable level shifter, turn on 1V8 and 3V3

    - turn on slow clock (comes from msp430)

    - 26 Mhz crystal should start oscillating

    - delay couple of milliseconds

    - make nshutdown high.

    - After a while the RTS pin should go low. 

    But there are 2 problems:

    - 26 Mhz crystal never starts oscillating.

    - RTS pin never goes low. In fact RTS pin also never reaches 1V8 but is around 0.6V and stays there.

    Is there some malfuntion in hardware? 

  • Hi,

    Can you please try to source the fast and slow clock externally and try. Please refer to the data sheet for more details on the accuracy of the clock

  • Hello! May be you can help to solve our problem?

    We have a problems with MSP430F5229 and CC2564B. All works at MSP430F5438, but at 5229 power up sequence is OK and RTS goes low, rx/tx starting,  but the stack is not initialized (by Result = BSC_Initialize (HCI_DriverInformation, 0) returns Result = -4 (we need 0). And BSC Initialize - compiled into the library, so its difficult to understand what is wrong.

    So all done by Hardware Porting Guidelines.pdf from stonestreetone,

    Thanks.4130.8468.HRDWCFG.h

  • Hi,

    Error -4 is defined as BTPS_ERROR_HCI_INITIALIZATION_ERROR, which means that you uart is not configured correctly.
    Please make sure first three steps mentioned here http://processors.wiki.ti.com/index.php/CC256x_Testing_Guide are followed.

    From the file you have shared I did not get the BT_DEBUG_UART_PIN_TX_MASK (TX_MASK) configuration? I did not see 5.6 and 5.7 in MSP430F5229 datasheet. 

  • Hi! Thank you for your quick reply! 

    as for first part of your message - we have no problem with it. This steps work. As for second - we don't use _DEBUG_UART 

    Please look at attachment.

    Thanks.

    4314.HAL.c
    /*****< HARDWARE.c >**********************************************************/
    /*      Copyright 2010 - 2014 Stonestreet One.                               */
    /*      All Rights Reserved.                                                 */
    /*                                                                           */
    /*  HARDWARE - Hardware API for MSP430 Experimentor Board                    */
    /*                                                                           */
    /*  Author:  Tim Cook                                                        */
    /*                                                                           */
    /*** MODIFICATION HISTORY ****************************************************/
    /*                                                                           */
    /*   mm/dd/yy  F. Lastname    Description of Modification                    */
    /*   --------  -----------    -----------------------------------------------*/
    /*   07/07/10  Tim Cook       Initial creation.                              */
    /*****************************************************************************/
    #include <msp430.h>
    #include <string.h>
    #include "HAL.h"                 /* MSP430 Hardware Abstraction API.         */
    #include "HRDWCFG.h"             /* SS1 MSP430 Hardware Configuration Header.*/
    #include "BTPSKRNL.h"
    
    #define BTPS_MSP430_DEFAULT_BAUD           115200L  /* Default UART Baud Rate*/
                                                        /* used in baud rate     */
                                                        /* given to this module  */
                                                        /* is invalid.           */
    
       /* The following are some defines that we will define to be 0 if they*/
       /* are not define in the device header.                              */
    
    #ifndef XT1LFOFFG
    
       #define XT1LFOFFG   0
    
    #endif
    
    #ifndef XT1HFOFFG
    
       #define XT1HFOFFG   0
    
    #endif
    
    #ifndef XT2OFFG
    
       #define XT2OFFG     0
    
    #endif
    
       /* Auxilary clock frequency                                          */
    #define ACLK_FREQUENCY_HZ  ((unsigned int)32768)
    
       /* Macro to do a floating point divide.                              */
    #define FLOAT_DIVIDE(x,y)  (((float)x)/((float)y))
    
       /* Macro to stop the OS Scheduler.                                   */
    #define STOP_SCHEDULER()   (TA1CTL &= (~(MC_3)))
    
       /* Instruction to start the Scheduler Tick ISR.                      */
    #define START_SCHEDULER()  (TA1CTL |= MC_1)
    
       /* The following structure represents the data that is stored to     */
       /* allow us to table drive the CPU setup for each of the Clock       */
       /* Frequencies that we allow.                                        */
    typedef struct _tagFrequency_Settings_t
    {
       unsigned char VCORE_Level;
       unsigned int  DCO_Multiplier;
    } Frequency_Settings_t;
    
       /* Internal Variables to this Module (Remember that all variables    */
       /* declared static are initialized to 0 automatically by the         */
       /* compiler as part of standard C/C++).                              */
    
                                  /* The following variable is used to hold */
                                  /* a system tick count for the Bluetopia  */
                                  /* No-OS stack.                           */
    static volatile unsigned long MSP430Ticks;
    
                                  /* The following function is provided to  */
                                  /* keep track of the number of peripherals*/
                                  /* that have requested that the SMCLK stay*/
                                  /* active. When this decrements to ZERO,  */
                                  /* the clock will be turned off.          */
    static volatile unsigned char ClockRequestedPeripherals;
    
                                  /* The following is used to buffer        */
                                  /* characters read from the Debug UART.   */
    //static unsigned char RecvBuffer[BT_DEBUG_UART_RX_BUFFER_SIZE];
    
                                  /* The following are used to track the    */
                                  /* Receive circular buffer.               */
    //static unsigned int  RxInIndex;
    //static unsigned int  RxOutIndex;
    //static unsigned int  RxBytesFree = BT_DEBUG_UART_RX_BUFFER_SIZE;
    
       /* If no buffer is specified, the this will result in a Blocking     */
       /* Write.                                                            */
    //#if BT_DEBUG_UART_TX_BUFFER_SIZE > 0
    
                                  /* The following is used to buffer        */
                                  /* characters sent to the Debug UART.     */
    //static unsigned char TransBuffer[BT_DEBUG_UART_TX_BUFFER_SIZE];
    
                                  /* The following are used to track the    */
                                  /* Transmir circular buffer.              */
    //static unsigned int TxInIndex;
    //static unsigned int TxOutIndex;
    //static unsigned int TxBytesFree = BT_DEBUG_UART_TX_BUFFER_SIZE;
    
    //#endif
    
       /* The following represents the table that we use to table drive the */
       /* CPU Frequency setup.                                              */
    static BTPSCONST Frequency_Settings_t Frequency_Settings[] =
    {
       {PMMCOREV_0, 244},  /* cf8MHZ_t.                          */
       {PMMCOREV_1, 488},  /* cf16MHZ_t.                         */
       {PMMCOREV_2, 610},  /* cf20MHZ_t.                         */
       {PMMCOREV_3, 675}   /* cf22.1184MHZ_t.                    */
    };
    
       /* External functions called by this module.  These are neccessary   */
       /* for UART operation and reside in HCITRANS.c                       */
    
       /* Called upon reception of a CTS Interrupt. Must toggle Interrupt   */
       /* Edge Polarity and flag Tx Flow Enabled State.                     */
    extern int CtsInterrupt(void);
    
       /* Local Function Prototypes.                                        */
    static Boolean_t DetermineProcessorType(void);
    static void ConfigureBoardDefaults(void);
    static void ConfigureLEDs(void);
    static void ToggleLED(int LEDID);
    static void SetLED(int LED_ID, int State);
    static void ConfigureTimer(void);
    static unsigned char IncrementVCORE(unsigned char Level);
    static unsigned char DecrementVCORE(unsigned char Level);
    static void ConfigureVCore(unsigned char Level);
    static void StartCrystalOscillator(void);
    static void SetSystemClock(Cpu_Frequency_t CPU_Frequency);
    
       /* The following function is responsible for determining if we are   */
       /* running on the MSP430F5438 or the MSP430F5438A processor.  This   */
       /* function returns TRUE if we are on the MSP430F5438A or FALSE      */
       /* otherwise.                                                        */
    static Boolean_t DetermineProcessorType(void)
    {
      return(TRUE);
    }
    
    /* The following function is used to configure all unused pins to    */
    /* their board default values.                                       */
    static void ConfigureBoardDefaults(void)
    {
    ///P1.0 - ACLC out/////////////////////////////////////////////////////////////////////////////
    /*
    P1SEL |=  BIT0; // Bit = 1: Peripheral module function is selected for the pin (ACLK)
    P1DIR |=  BIT0; // Bit = 1b = Port configured as output
    P1DS  |=  BIT0;//1b = Full output drive strength
    P1REN &= ~BIT0;//0b = Pullup or pulldown disabled 
    P1OUT &= ~BIT0; //0b = Output is low
    */
    ///////////////////////////////////////////////////////////////////////////////////////////////
    ///P1.1 - trigger - ������ ������� ���������� ����. ����� (IN)
    P1SEL &= ~(BIT6 | BIT7);//0b = I/O function is selected
    P1DIR &= ~(BIT6 | BIT7);//0b = Port configured as input
    P1REN &= ~BIT1;//Bit = 0: Pullup/pulldown resistor disabled
    P1OUT &= ~BIT1;//Bit = 0: Output is low
    P1DS  &= ~BIT1;//Bit = 0: Reduced drive strength
    //����������
    P1IES &= ~BIT1; //Bit = 0: Respective PxIFG flag is set with a low-to-high transition 
    P1IE  |=  BIT1; //���������� ��������� 
    P1IFG = 0;
    ///////////////////////////////////////////////////////////////////////////////////////////////
    ///P1.2 - DRIVE DRIG - ��������� ������ ����. �����. - OUT
    P1SEL &= ~BIT2;//0b = I/O function is selected   
    P1DIR |=  BIT2;//1b = Port configured as output
    P1DS  &= ~BIT2;//Bit = 0: Reduced drive strength
    P1REN &= ~BIT2;//0b = Pullup or pulldown disabled   
    //P1OUT &= ~BIT2; //0b = Output is low
    P1OUT |=  BIT2; //Bit = 1: Output is high
    ///////////////////////////////////////////////////////////////////////////////////////////////
    ///P1.3 - BUTTON PRESSED - ��������� ������� ����� - IN
    P1SEL &= ~BIT3;//0b = I/O function is selected
    P1DIR &= ~BIT3;//0b = Port configured as input
    //
    P1REN &= ~BIT3;//Bit = 0: Pullup/pulldown resistor disabled
    P1OUT &= ~BIT3;//Bit = 0: Output is low
    P1DS  &= ~BIT3;//Bit = 0: Reduced drive strength
    //����������
    P1IES &= ~BIT3; //Bit = 0: Respective PxIFG flag is set with a low-to-high transition 
    P1IE  |=  BIT3; //���������� ��������� 
    P1IFG = 0;
    ///////////////////////////////////////////////////////////////////////////////////////////////
    ///P1.5 - B� CTS - OUT/////////////////////////////////////////////////////////////////////////
    ///P1.6 - B� RTS - IN WITH low-to-high INT ENABLED
    //P2 - �� ������������
    //P3 -������ ���� ������ ��������� ����� ��������� ����� ������(�� �����)
    //P4.6 - B� SHUTD - ����� ������ - ������ -  OUT -  ��������� ����� ��������� ����� ������(�� �����)- ����� - �������� �������
    /*P4SEL &= ~BIT6;//0b = I/O function is selected   
    P4DIR |=  BIT6;//1b = Port configured as output
    P4DS  &= ~BIT6;//Bit = 0: Reduced drive strength
    P4REN &= ~BIT6;//0b = Pullup or pulldown disabled   
    //P1OUT &= ~BIT6; //0b = Output is low
    P4OUT |=  BIT6; //Bit = 1: Output is high*/
    /////////////////////////////////////////////////////////////////////////////////////////////////
    ///P5.1 - POWER HOLD - ��������� ������� ���� ����� - OUT
    P5SEL &= ~BIT6;//0b = I/O function is selected   
    P5DIR |=  BIT6;//1b = Port configured as output
    P5DS  &= ~BIT6;//Bit = 0: Reduced drive strength
    P5REN &= ~BIT6;//0b = Pullup or pulldown disabled   
    P5OUT |=  BIT6; //Bit = 1: Output is high - ���� �������
    /////////////////////////////////////////////////////////////////////////////////////////////////
    ///P5.4 - P5.5 - ����� ��� ������ - �������� �� ����� 
    /////////////////////////////////////////////////////////////////////////////////////////////////
    ///P6.4 P6.7 - ���������� - ������ �� �����
    //����� ������� ��������� �����
    // P7.0 - Track1+
    P7SEL &= ~BIT0;//0b = I/O function is selected   
    P7DIR |=  BIT0;//1b = Port configured as output
    P7DS  |=  BIT0;//Bit = 1: Full drive strength
    P7REN &= ~BIT0;//0b = Pullup or pulldown disabled   
    //P7OUT |=  BIT0; //Bit = 1: Output is high - ���� �������
    P7OUT &= ~BIT0; //0b = Output is low - ���� ��������
    /////////////////////////////////////////////////////////////////////////////////////////////////
    // P7.5 - Track1-
    P7SEL &= ~BIT5;//0b = I/O function is selected   
    P7DIR |=  BIT5;//1b = Port configured as output
    P7DS  |=  BIT5;//Bit = 1: Full drive strength
    P7REN &= ~BIT5;//0b = Pullup or pulldown disabled   
    //P7OUT |=  BIT0; //Bit = 1: Output is high - ���� �������
    P7OUT &= ~BIT5; //0b = Output is low - ���� ��������
    /////////////////////////////////////////////////////////////////////////////////////////////////
    // P7.3 - Track2+
    P7SEL &= ~BIT3;//0b = I/O function is selected   
    P7DIR |=  BIT3;//1b = Port configured as output
    P7DS  |=  BIT3;//Bit = 1: Full drive strength
    P7REN &= ~BIT3;//0b = Pullup or pulldown disabled   
    //P7OUT |=  BIT0; //Bit = 1: Output is high - ���� �������
    P7OUT &= ~BIT3; //0b = Output is low - ���� ��������
    /////////////////////////////////////////////////////////////////////////////////////////////////
    // P7.1 - Track2-
    P7SEL &= ~BIT1;//0b = I/O function is selected   
    P7DIR |=  BIT1;//1b = Port configured as output
    P7DS  |=  BIT1;//Bit = 1: Full drive strength
    P7REN &= ~BIT1;//0b = Pullup or pulldown disabled   
    //P7OUT |=  BIT0; //Bit = 1: Output is high - ���� �������
    P7OUT &= ~BIT1; //0b = Output is low - ���� ��������
    /////////////////////////////////////////////////////////////////////////////////////////////////
    }
    
    /* The following function is used to configure the board LEDs.       */
    static void ConfigureLEDs(void)
    {
    ///P6.4 -LED BLUE- ��������� ������?  - OUT
    P6SEL &= ~BIT4;//0b = I/O function is selected   
    P6DIR |=  BIT4;//1b = Port configured as output
    P6DS  |=  BIT4;//Bit = 1: Full drive strength
    P6REN &= ~BIT4;//0b = Pullup or pulldown disabled   
    P6OUT |=  BIT4; //Bit = 1: Output is high - ���� �������
    /////////////////////////////////////////////////////////////////////////////////////////////////
    ///P6.7 -LED Red- ����� �����- ����  - OUT
    P6SEL &= ~BIT7;//0b = I/O function is selected   
    P6DIR |=  BIT7;//1b = Port configured as output
    P6DS  |=  BIT7;//Bit = 1: Full drive strength
    P6REN &= ~BIT7;//0b = Pullup or pulldown disabled   
    P6OUT &= ~BIT7; //0b = Output is low - ���� ��������
    }
    
    /* The following function is a utility function used to toggle an    */
    /* BLUE LED.                                                              */
    static void ToggleLED(int LEDID)
    {
    P6OUT ^=  BIT4; //
    }
    
    /* The following function is a utility function that is used to set  */
    /* the state of a specified LED.  
    LED_ID - (LED BLUE = BIT4) (LED RED = BIT7) */
    static void SetLED(int LED_ID, int State)
    {
      if(State)
         P6OUT |=  LED_ID;
      else
         P6OUT &= ~LED_ID;
    }
    
       /* This function is called to configure the System Timer, i.e TA1.   */
       /* This timer is used for all system time scheduling.                */
    static void ConfigureTimer(void)
    {
       /* Ensure the timer is stopped.                                      */
       TA1CTL = 0;
    
       /* Run the timer off of the ACLK.                                    */
       TA1CTL = TASSEL_1 | ID_0;
    
       /* Clear everything to start with.                                   */
       TA1CTL |= TACLR;
    
       /* Set the compare match value according to the tick rate we want.   */
       TA1CCR0 = ( ACLK_FREQUENCY_HZ / MSP430_TICK_RATE_HZ ) + 1;
    
       /* Enable the interrupts.                                            */
       TA1CCTL0 = CCIE;
    
       /* Start up clean.                                                   */
       TA1CTL |= TACLR;
    
       /* Up mode.                                                          */
       TA1CTL |= TASSEL_1 | MC_1 | ID_0;
    }
    
       /* The following function is a utility function the is used to       */
       /* increment the VCore setting to the specified value.               */
    static unsigned char IncrementVCORE(unsigned char Level)
    {
       unsigned char Result;
       unsigned char PMMRIE_backup;
       unsigned char SVSMHCTL_backup;
       unsigned char SVSMLCTL_backup;
    
       /* The code flow for increasing the Vcore has been altered to work   */
       /* around the erratum FLASH37.  Please refer to the Errata sheet to  */
       /* know if a specific device is affected DO NOT ALTER THIS FUNCTION  */
    
       /* Open PMM registers for write access.                              */
       PMMCTL0_H     = 0xA5;
    
       /* Disable dedicated Interrupts and backup all registers.            */
       PMMRIE_backup    = PMMRIE;
       PMMRIE          &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | SVSLPE | SVMHVLRIE | SVMHIE | SVSMHDLYIE | SVMLVLRIE | SVMLIE | SVSMLDLYIE );
       SVSMHCTL_backup  = SVSMHCTL;
       SVSMLCTL_backup  = SVSMLCTL;
    
       /* Clear flags.                                                      */
       PMMIFG           = 0;
    
       /* Set SVM highside to new level and check if a VCore increase is    */
       /* possible.                                                         */
       SVSMHCTL = SVMHE | SVSHE | (SVSMHRRL0 * Level);
    
       /* Wait until SVM highside is settled.                               */
       while ((PMMIFG & SVSMHDLYIFG) == 0);
    
       /* Clear flag.                                                       */
       PMMIFG &= ~SVSMHDLYIFG;
    
       /* Check if a VCore increase is possible.                            */
       if((PMMIFG & SVMHIFG) == SVMHIFG)
       {
          /* Vcc is too low for a Vcore increase so we will recover the     */
          /* previous settings                                              */
          PMMIFG &= ~SVSMHDLYIFG;
          SVSMHCTL = SVSMHCTL_backup;
    
          /* Wait until SVM highside is settled.                            */
          while ((PMMIFG & SVSMHDLYIFG) == 0)
             ;
    
          /* Return that the value was not set.                             */
          Result = 1;
       }
       else
       {
          /* Set also SVS highside to new level Vcc is high enough for a    */
          /* Vcore increase                                                 */
          SVSMHCTL |= (SVSHRVL0 * Level);
    
          /* Wait until SVM highside is settled.                            */
          while ((PMMIFG & SVSMHDLYIFG) == 0)
             ;
    
          /* Clear flags.                                                   */
          PMMIFG &= ~SVSMHDLYIFG;
    
          /* Set VCore to new level.                                        */
          PMMCTL0_L = PMMCOREV0 * Level;
    
          /* Set SVM, SVS low side to new level.                            */
          SVSMLCTL = SVMLE | (SVSMLRRL0 * Level) | SVSLE | (SVSLRVL0 * Level);
    
          /* Wait until SVM, SVS low side is settled.                       */
          while ((PMMIFG & SVSMLDLYIFG) == 0)
             ;
    
          /* Clear flag.                                                    */
          PMMIFG &= ~SVSMLDLYIFG;
    
          /* SVS, SVM core and high side are now set to protect for the new */
          /* core level.  Restore Low side settings Clear all other bits    */
          /* _except_ level settings                                        */
          SVSMLCTL &= (SVSLRVL0+SVSLRVL1+SVSMLRRL0+SVSMLRRL1+SVSMLRRL2);
    
          /* Clear level settings in the backup register,keep all other     */
          /* bits.                                                          */
          SVSMLCTL_backup &= ~(SVSLRVL0+SVSLRVL1+SVSMLRRL0+SVSMLRRL1+SVSMLRRL2);
    
          /* Restore low-side SVS monitor settings.                         */
          SVSMLCTL |= SVSMLCTL_backup;
    
          /* Restore High side settings.  Clear all other bits except level */
          /* settings                                                       */
          SVSMHCTL &= (SVSHRVL0+SVSHRVL1+SVSMHRRL0+SVSMHRRL1+SVSMHRRL2);
    
          /* Clear level settings in the backup register,keep all other     */
          /* bits.                                                          */
          SVSMHCTL_backup &= ~(SVSHRVL0+SVSHRVL1+SVSMHRRL0+SVSMHRRL1+SVSMHRRL2);
    
          /* Restore backup.                                                */
          SVSMHCTL |= SVSMHCTL_backup;
    
          /* Wait until high side, low side settled.                        */
          while(((PMMIFG & SVSMLDLYIFG) == 0) && ((PMMIFG & SVSMHDLYIFG) == 0))
             ;
    
          /* Return that the value was set.                                 */
          Result = 0;
       }
    
       /* Clear all Flags.                                                  */
       PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);
    
       /* Restore PMM interrupt enable register.                            */
       PMMRIE = PMMRIE_backup;
    
       /* Lock PMM registers for write access.                              */
       PMMCTL0_H = 0x00;
    
       return(Result);
    }
    
       /* The following function is a utility function the is used to       */
       /* decrement the VCore setting to the specified value.               */
    static unsigned char DecrementVCORE(unsigned char Level)
    {
       unsigned char Result;
       unsigned char PMMRIE_backup;
       unsigned char SVSMHCTL_backup;
       unsigned char SVSMLCTL_backup;
    
       /* The code flow for decreasing the Vcore has been altered to work   */
       /* around the erratum FLASH37.  Please refer to the Errata sheet to  */
       /* know if a specific device is affected DO NOT ALTER THIS FUNCTION  */
    
       /* Open PMM registers for write access.                              */
       PMMCTL0_H        = 0xA5;
    
       /* Disable dedicated Interrupts Backup all registers                 */
       PMMRIE_backup    = PMMRIE;
       PMMRIE          &= ~(SVMHVLRPE | SVSHPE | SVMLVLRPE | SVSLPE | SVMHVLRIE | SVMHIE | SVSMHDLYIE | SVMLVLRIE | SVMLIE | SVSMLDLYIE );
       SVSMHCTL_backup  = SVSMHCTL;
       SVSMLCTL_backup  = SVSMLCTL;
    
       /* Clear flags.                                                      */
       PMMIFG &= ~(SVMHIFG | SVSMHDLYIFG | SVMLIFG | SVSMLDLYIFG);
    
       /* Set SVM, SVS high & low side to new settings in normal mode.      */
       SVSMHCTL = SVMHE | (SVSMHRRL0 * Level) | SVSHE | (SVSHRVL0 * Level);
       SVSMLCTL = SVMLE | (SVSMLRRL0 * Level) | SVSLE | (SVSLRVL0 * Level);
    
       /* Wait until SVM high side and SVM low side is settled.             */
       while (((PMMIFG & SVSMHDLYIFG) == 0) || ((PMMIFG & SVSMLDLYIFG) == 0))
          ;
    
       /* Clear flags.                                                      */
       PMMIFG &= ~(SVSMHDLYIFG + SVSMLDLYIFG);
    
       /* SVS, SVM core and high side are now set to protect for the new    */
       /* core level.                                                       */
    
       /* Set VCore to new level.                                           */
       PMMCTL0_L = PMMCOREV0 * Level;
    
       /* Restore Low side settings Clear all other bits _except_ level     */
       /* settings                                                          */
       SVSMLCTL &= (SVSLRVL0+SVSLRVL1+SVSMLRRL0+SVSMLRRL1+SVSMLRRL2);
    
       /* Clear level settings in the backup register,keep all other bits.  */
       SVSMLCTL_backup &= ~(SVSLRVL0+SVSLRVL1+SVSMLRRL0+SVSMLRRL1+SVSMLRRL2);
    
       /* Restore low-side SVS monitor settings.                            */
       SVSMLCTL |= SVSMLCTL_backup;
    
       /* Restore High side settings Clear all other bits except level      */
       /* settings                                                          */
       SVSMHCTL &= (SVSHRVL0+SVSHRVL1+SVSMHRRL0+SVSMHRRL1+SVSMHRRL2);
    
       /* Clear level settings in the backup register, keep all other bits. */
       SVSMHCTL_backup &= ~(SVSHRVL0+SVSHRVL1+SVSMHRRL0+SVSMHRRL1+SVSMHRRL2);
    
       /* Restore backup.                                                   */
       SVSMHCTL |= SVSMHCTL_backup;
    
       /* Wait until high side, low side settled.                           */
       while (((PMMIFG & SVSMLDLYIFG) == 0) && ((PMMIFG & SVSMHDLYIFG) == 0))
          ;
    
       /* Clear all Flags.                                                  */
       PMMIFG &= ~(SVMHVLRIFG | SVMHIFG | SVSMHDLYIFG | SVMLVLRIFG | SVMLIFG | SVSMLDLYIFG);
    
       /* Restore PMM interrupt enable register.                            */
       PMMRIE = PMMRIE_backup;
    
       /* Lock PMM registers for write access.                              */
       PMMCTL0_H = 0x00;
    
       /* Return success to the caller.                                     */
       Result    = 0;
    
       return(Result);
    }
    
       /* The following function is responsible for setting the PMM core    */
       /* voltage to the specified level.                                   */
    static void ConfigureVCore(unsigned char Level)
    {
       unsigned int ActualLevel;
       unsigned int Status;
    
       /* Set Mask for Max.  level.                                         */
       Level       &= PMMCOREV_3;
    
       /* Get actual VCore.                                                 */
       ActualLevel  = (PMMCTL0 & PMMCOREV_3);
    
       /* Step by step increase or decrease the VCore setting.              */
       Status = 0;
       while (((Level != ActualLevel) && (Status == 0)) || (Level < ActualLevel))
       {
         if (Level > ActualLevel)
           Status = IncrementVCORE(++ActualLevel);
         else
           Status = DecrementVCORE(--ActualLevel);
       }
    }
    
       /* The following function is responsible for starting XT1 in the     */
       /* MSP430 that is used to source the internal FLL that drives the    */
       /* MCLK and SMCLK.                                                   */
    static void StartCrystalOscillator(void)
    {
       /* Set up XT1 Pins to analog function, and to lowest drive           */
       P5SEL   |= (BIT4 | BIT5);
    
       /* Set internal cap values.                                          */
       UCSCTL6 |= XCAP_3;
    
       /* Loop while the Oscillator Fault bit is set.                       */
       while(SFRIFG1 & OFIFG)
       {
         while (SFRIFG1 & OFIFG)
         {
            /* Clear OSC fault flags.                                       */
           UCSCTL7 &= ~(DCOFFG + XT1LFOFFG + XT1HFOFFG + XT2OFFG);
           SFRIFG1 &= ~OFIFG;
         }
    
         /* Reduce the drive strength.                                      */
         UCSCTL6 &= ~(XT1DRIVE1_L + XT1DRIVE0);
       }
    }
    
       /* The following function is responsible for setting up the system   */
       /* clock at a specified frequency.                                   */
    static void SetSystemClock(Cpu_Frequency_t CPU_Frequency)
    {
       Boolean_t                       UseDCO;
       unsigned int                    Ratio;
       unsigned int                    DCODivBits;
       unsigned long                   SystemFrequency;
       volatile unsigned int           Counter;
       BTPSCONST Frequency_Settings_t *CPU_Settings;
    
       /* Verify that the CPU Frequency enumerated type is valid, if it is  */
       /* not then we will force it to a default.                           */
       if((CPU_Frequency != cf8MHZ_t) && (CPU_Frequency != cf16MHZ_t) && (CPU_Frequency != cf20MHZ_t) && (CPU_Frequency != cf25MHZ_t))
          CPU_Frequency = cf16MHZ_t;
    
       /* Do not allow improper settings (MSP430F5438 cannot run at 20MHz or*/
       /* 25 MHz).                                                          */
       if((!DetermineProcessorType()) && ((CPU_Frequency == cf20MHZ_t) || (CPU_Frequency == cf25MHZ_t)))
          CPU_Frequency = cf16MHZ_t;
    
       /* Get the CPU settings for the specified frequency.                 */
       CPU_Settings = &Frequency_Settings[CPU_Frequency - cf8MHZ_t];
    
       /* Configure the PMM core voltage.                                   */
       ConfigureVCore(CPU_Settings->VCORE_Level);
    
       /* Get the ratio of the system frequency to the source clock.        */
       Ratio           = CPU_Settings->DCO_Multiplier;
    
       /* Use a divider of at least 2 in the FLL control loop.              */
       DCODivBits      = FLLD__2;
    
       /* Get the system frequency that is configured.                      */
       SystemFrequency  = HAL_GetSystemSpeed();
       SystemFrequency /= 1000;
    
       /* If the requested frequency is above 16MHz we will use DCO as the  */
       /* source of the system clocks, otherwise we will use DCOCLKDIV.     */
       if(SystemFrequency > 16000)
       {
           Ratio  >>= 1;
           UseDCO   = TRUE;
       }
       else
       {
           SystemFrequency <<= 1;
           UseDCO            = FALSE;
       }
    
       /* While needed set next higher div level.                           */
       while (Ratio > 512)
       {
           DCODivBits   = DCODivBits + FLLD0;
           Ratio      >>= 1;
       }
    
       /* Disable the FLL.                                                  */
       __bis_SR_register(SCG0);
    
       /* Set DCO to lowest Tap.                                            */
       UCSCTL0 = 0x0000;
    
       /* Reset FN bits.                                                    */
       UCSCTL2 &= ~(0x03FF);
       UCSCTL2  = (DCODivBits | (Ratio - 1));
    
       /* Set the DCO Range.                                                */
       if(SystemFrequency <= 630)
       {
          /* Fsystem < 630KHz.                                              */
          UCSCTL1 = DCORSEL_0;
       }
       else if(SystemFrequency <  1250)
       {
          /* 0.63MHz < fsystem < 1.25MHz.                                   */
          UCSCTL1 = DCORSEL_1;
       }
       else if(SystemFrequency <  2500)
       {
          /* 1.25MHz < fsystem < 2.5MHz.                                    */
          UCSCTL1 = DCORSEL_2;
       }
       else if(SystemFrequency <  5000)
       {
          /* 2.5MHz < fsystem < 5MHz.                                       */
          UCSCTL1 = DCORSEL_3;
       }
       else if(SystemFrequency <  10000)
       {
          /* 5MHz < fsystem < 10MHz.                                        */
          UCSCTL1 = DCORSEL_4;
       }
       else if(SystemFrequency <  20000)
       {
          /* 10MHz < fsystem < 20MHz.                                       */
          UCSCTL1 = DCORSEL_5;
       }
       else if(SystemFrequency <  40000)
       {
          /* 20MHz < fsystem < 40MHz.                                       */
          UCSCTL1 = DCORSEL_6;
       }
       else
          UCSCTL1 = DCORSEL_7;
    
       /* Re-enable the FLL.                                                */
       __bic_SR_register(SCG0);
    
       /* Loop until the DCO is stabilized.                                 */
       while(UCSCTL7 & DCOFFG)
       {
           /* Clear DCO Fault Flag.                                         */
           UCSCTL7 &= ~DCOFFG;
    
           /* Clear OFIFG fault flag.                                       */
           SFRIFG1 &= ~OFIFG;
       }
    
       /* Enable the FLL control loop.                                      */
       __bic_SR_register(SCG0);
    
       /* Based on the frequency we will use either DCO or DCOCLKDIV as the */
       /* source of MCLK and SMCLK.                                         */
       if (UseDCO)
       {
          /* Select DCOCLK for MCLK and SMCLK.                              */
          UCSCTL4 &=  ~(SELM_7 | SELS_7);
          UCSCTL4 |= (SELM__DCOCLK | SELS__DCOCLK);
       }
       else
       {
          /* Select DCOCLKDIV for MCLK and SMCLK.                           */
           UCSCTL4 &=  ~(SELM_7 | SELS_7);
           UCSCTL4 |= (SELM__DCOCLKDIV | SELS__DCOCLKDIV);
       }
    
       /* Delay the appropriate amount of cycles for the clock to settle.   */
       Counter = Ratio * 32;
       while (Counter--)
           __delay_cycles(30);
    }
    
       /* The following function is provided to allow a mechanism of        */
       /* configuring the MSP430 pins to their default state for the sample.*/
    void HAL_ConfigureHardware(void)
    {
       /* Configure the default board setup.                                */
      // ConfigureBoardDefaults();
    
       /* Configure the LEDs for outputs                                    */
     //  ConfigureLEDs();
    
       /* Call the MSP430F5438 Experimentor Board Hardware Abstraction Layer*/
       /* to setup the system clock.                                        */
       StartCrystalOscillator();
       SetSystemClock(BT_CPU_FREQ);
    
       /* Configure the UART-USB Port for its default configuration         */
    //   HAL_CommConfigure(BT_DEBUG_UART_BASE, BT_DEBUG_UART_BAUDRATE, 0);
    //   GPIOPinTypeUART(BT_DEBUG_UART_PIN_BASE, BT_DEBUG_UART_PIN_TX_MASK, BT_DEBUG_UART_PIN_RX_MASK);
    
       /* Enable Debug UART Receive Interrupt.                              */
    //   UARTIntEnableReceive(BT_DEBUG_UART_BASE);
    
       /* Configure the scheduler timer.                                    */
          ConfigureTimer();
    }
    
       /* * NOTE * The following are the allowed flags for the flags        */
       /*          argument.                                                */
       /*  1.  UART_CONFIG_WLEN_8, UART_CONFIG_WLEN_7                       */
       /*  2.  UART_CONFIG_PAR_NONE,UART_CONFIG_PAR_ODD,UART_CONFIG_PAR_EVEN*/
       /*  3.  UART_CONFIG_STOP_ONE,UART_CONFIG_STOP_TWO                    */
       /*          The flags is a bitfield which may include one flag from  */
       /*          each of the three rows above                             */
    void HAL_CommConfigure(unsigned char *UartBase, unsigned long BaudRate, unsigned char Flags)
    {
       float          division_factor;
       unsigned int   brf;
       unsigned long  Frequency;
    
       /* Since we allow access to register clear any invalid flags.        */
       Flags &= ~(UART_CONFIG_PAR_EVEN | UART_CONFIG_WLEN_7 | UART_CONFIG_STOP_TWO);
    
       /* set UCSWRST bit to hold UART module in reset while we configure   */
       /* it.                                                               */
       HWREG8(UartBase + MSP430_UART_CTL1_OFFSET) = MSP430_UART_CTL1_SWRST;
    
       /* Configure control register 0 by clearing and then setting the     */
       /* allowed user options we also ensure that UCSYNC = Asynchronous    */
       /* Mode, UCMODE = UART, UCMSB = LSB first and also ensure that the   */
       /* default 8N1 configuration is used if the flags argument is 0.     */
       HWREG8(UartBase + MSP430_UART_CTL0_OFFSET) = Flags;
    
       /* UART peripheral erroneous characters cause interrupts break       */
       /* characters cause interrupts on reception                          */
       HWREG8(UartBase + MSP430_UART_CTL1_OFFSET) |= (MSP430_UART_CTL1_RXIE | MSP430_UART_CTL1_BRKIE);
    
       /* clear UCA status register                                         */
       HWREG8(UartBase + MSP430_UART_STAT_OFFSET)  = 0x00;
    
       /* clear interrupt flags                                             */
       HWREG8(UartBase + MSP430_UART_IFG_OFFSET)  &= ~(MSP430_UART_TXIFG_mask | MSP430_UART_RXIFG_mask);
    
       /* check to see if the baud rate is valid, if not then use a default.*/
       if(BaudRate)
       {
          /* Use ACLK for Baud rates less than 9600 to allow us to still    */
          /* receive characters while in LPM3.                              */
          if(BaudRate <= 9600)
          {
             HWREG8(UartBase + MSP430_UART_CTL1_OFFSET) |= MSP430_UART_CTL1_UCSSEL_ACLK_mask;
             Frequency = ACLK_FREQUENCY_HZ;
          }
          else
          {
             HWREG8(UartBase + MSP430_UART_CTL1_OFFSET) |= MSP430_UART_CTL1_UCSSEL_SMCLK_mask;
             Frequency = HAL_GetSystemSpeed();
          }
    
          division_factor = (FLOAT_DIVIDE(Frequency, BaudRate));
       }
       else
       {
          /* Get the system frequency.                                      */
          Frequency = HAL_GetSystemSpeed();
    
          /* If the baud rate is not valid we will use a default.           */
          HWREG8(UartBase + MSP430_UART_CTL1_OFFSET) |= MSP430_UART_CTL1_UCSSEL_SMCLK_mask;
          division_factor = (FLOAT_DIVIDE(Frequency, BTPS_MSP430_DEFAULT_BAUD));
       }
    
       /* Set up the modulation stages and oversampling mode.               */
       HWREG8(UartBase + MSP430_UART_MCTL_OFFSET) = 0;
       if((division_factor >= 16) && (BaudRate < 921600L))
       {
          /* we will use oversampling mode and formulas as in sect 19.3.10.2*/
          /* of MSP430x5xx Family Users Guide                               */
          HWREG16(UartBase + MSP430_UART_BRW_OFFSET) = (unsigned int) (division_factor / 16);
    
          /* forumla for BRF specifies rounding up which is why 0.5 is added*/
          /* before casting to int since C integer casts truncate           */
          brf                                        = ((unsigned int)((((FLOAT_DIVIDE(division_factor, 16))-((unsigned int)(FLOAT_DIVIDE(division_factor, 16))))*16)+0.5));
    
          /* set the correct BRF, then set BRS to 0 (may need this later),  */
          /* then enable oversampling mode                                  */
          HWREG8(UartBase + MSP430_UART_MCTL_OFFSET) = (((brf << MSP430_UART_MCTL_BRF_bit) & MSP430_UART_MCTL_BRF_MASK) | MSP430_UART_MCTL_UCOS16_mask);
       }
       else
       {
          /* we will use oversampling mode and formulas as in sect 19.3.10.1*/
          /* of MSP430x5xx Family Users Guide section 19.3.10.1 specifies   */
          /* setting UCBRS and clearing UCOS16 bit.                         */
          HWREG16(UartBase + MSP430_UART_BRW_OFFSET)  = (unsigned int)division_factor;
          brf                                         = ((unsigned int)(((division_factor - ((unsigned int)division_factor))*8) + 0.5));
    
          /* Set the proper BRS field                                       */
          HWREG8(UartBase + MSP430_UART_MCTL_OFFSET)  = ((brf << MSP430_UART_MCTL_BRS_bit) & MSP430_UART_MCTL_BRS_MASK);
          HWREG8(UartBase + MSP430_UART_MCTL_OFFSET) &= (~(MSP430_UART_MCTL_UCOS16_mask));
       }
    
       /* now clear the UCA2 Software Reset bit                             */
       HWREG8(UartBase + MSP430_UART_CTL1_OFFSET) &= (~(MSP430_UART_CTL1_SWRST));
    }
    
    
       /* The following function is used to return the configured system    */
       /* clock speed in MHz.                                               */
    unsigned long HAL_GetSystemSpeed(void)
    {
       Cpu_Frequency_t Frequency;
    
       /* Verify that the CPU Frequency enumerated type is valid, if it is  */
       /* not then we will force it to a default.                           */
       if((BT_CPU_FREQ != cf8MHZ_t) && (BT_CPU_FREQ != cf16MHZ_t) && (BT_CPU_FREQ != cf20MHZ_t) && (BT_CPU_FREQ != cf25MHZ_t))
          Frequency = cf16MHZ_t;
       else
          Frequency = BT_CPU_FREQ;
    
       if((!DetermineProcessorType()) && ((Frequency == cf20MHZ_t) || (Frequency == cf25MHZ_t)))
          return(((unsigned long)Frequency_Settings[cf16MHZ_t - cf8MHZ_t].DCO_Multiplier) * 32768L);
       else
          return(((unsigned long)Frequency_Settings[Frequency - cf8MHZ_t].DCO_Multiplier) * 32768L);
    }
    
       /* This function is called to get the system Tick Count.             */
    unsigned long HAL_GetTickCount(void)
    {
       return(MSP430Ticks);
    }
    
       /* The following Toggles an LED at a passed in blink rate.           */
    void HAL_LedToggle(int LED_ID)
    {
       ToggleLED(0);
    }
    
       /* The following function is used to set an LED to a specified state.*/
    void HAL_SetLED(int LED_ID, int State)
    {
       SetLED(LED_ID, State);
    }
    
       /* The following function is called to enter LPM3 mode on the MSP    */
       /* with the OS Timer Tick Disabled.                                  */
    void HAL_LowPowerMode(unsigned char DisableLED)
    {
       /* Turn off Timer 1, which is used for the FreeRTOS and NoRTOS       */
       /* timers. The timer runs off of the Auxilary Clock (ACLK) thus      */
       /* without this the timer would continue to run, consuming power     */
       /* and waking up the processor every 1 ms. Enter a critical section  */
       /* to do so that we do get switched out by the OS in the middle of   */
       /* stopping the OS Scheduler.                                        */
       __disable_interrupt();
    
       STOP_SCHEDULER();
    
       /* Clear the count register.                                         */
       TA1R = 0;
    
       __enable_interrupt();
    
       /* Turn off the LEDs if requested. */
     if(DisableLED)
       {
          SetLED(0, 0);
          SetLED(1, 0);
       }
    
       /* Enter LPM3.                                                       */
       LPM3;
     
       /* Re-start the OS scheduler.                                        */
       START_SCHEDULER();
    
       /* Set the interrupt trigger bit to trigger an interrupt.            */
       TA1CCTL0 |= 0x01;
    }
    
       /* The following function is called to enable the SMCLK Peripheral   */
       /* on the MSP430.                                                    */
       /* * NOTE * This function should be called with interrupts disabled. */
    void HAL_EnableSMCLK(unsigned char Peripheral)
    {
       /* Note, we will only disable SMCLK Request if the Baud Rate for the */
       /* Debug Console is less than or equal to 9600 BAUD.                 */
    #if BT_DEBUG_UART_BAUDRATE <= 9600
    
       UCSCTL8                   |= SMCLKREQEN;
       ClockRequestedPeripherals |= Peripheral;
    
    #endif
    }
    
       /* The following function is called to disable the SMCLK Peripheral  */
       /* on the MSP430.                                                    */
       /* * NOTE * This function should be called with interrupts disabled. */
    void HAL_DisableSMCLK(unsigned char Peripheral)
    {
       /* Note, we will only disable SMCLK Request if the Baud Rate for the */
       /* Debug Console is less than or equal to 9600 BAUD.                 */
    #if BT_DEBUG_UART_BAUDRATE <= 9600
    
       ClockRequestedPeripherals &= ~Peripheral;
    
       if(!ClockRequestedPeripherals)
          UCSCTL8 &= ~SMCLKREQEN;
    
    #endif
    }
    
       /* Timer A Get Tick Count Function for BTPSKRNL Timer A Interrupt.   */
       /* Included for Non-OS builds                                        */
    #pragma vector=TIMER1_A0_VECTOR
    __interrupt void TIMER_INTERRUPT(void)
    {
       ++MSP430Ticks;
    
       /* Exit from LPM if necessary (this statement will have no effect if */
       /* we are not currently in low power mode).                          */
       LPM3_EXIT;
    }
    
       /* CTS Pin Interrupt. CtsInterrupt routine must change the polarity  */
       /* of the Cts Interrupt.                                             */
    #pragma vector=BT_UART_CTS_IV
    __interrupt void CTS_ISR(void)
    {
       switch(BT_UART_CTS_IVR)
       {
          case BT_UART_CTS_INT_NUM:
             if(CtsInterrupt())
             {
                /* Exit LPM3 on interrupt exit (RETI).                      */
                LPM3_EXIT;
    
             }
             break;
       }
    }
    
    #pragma vector=PORT2_VECTOR
    __interrupt void SW_1_2_ISR (void)
    {
    if (P2IFG  == 0x40) card_translation_steps();
    else bar_code_translation();  
    P2IFG  = 0;
    }
    
    char start_buttons_pressed(void)
    {
      if (P2IN &0x40 && P2IN &0x80) return 0;
      else return 1;
    }
    
    
    
    

  • Hi,

    I am also getting the same error code. I checked the startup procedure and found out that HCI_RTS is getting pulled low for about 2.5 seconds when nSHUTDOWN is pulled high. Do you have any thoughts on what could be going wrong?

    thanks,
    Sooraj
  • Hi Sooraj,

    Please refer to the following post.
    e2e.ti.com/.../562083

    Closing this thread to avoid duplicates.

    Best regards,
    Vihang