CC2564 PCM clock jitter issue

Ronie Oh

Expert 3145 points

Other Parts Discussed in Thread: MSP430F5438, CC2564

Hi champs,

My customer is working on CC2564 module with MSP430F5438 EVM and audio DAC.

Their audio DAC master clock is made by CC2564 PCM clock,and requires over 2.8 MHz in stable.

However, CC2564 PCM clock is following FSYNC clock so that there is jitter.

Is there any idea to generate PCM clock, any pin to generate 2.8Mhz in stable?

Thanks,

Ronie

over 9 years ago

0 Sundeep Javvaji over 9 years ago

TI__Mastermind 32615 points

Hi,

Let me check it internal and get back to you on this.

0 Sundeep Javvaji over 9 years ago in reply to Sundeep Javvaji

TI__Mastermind 32615 points

Hi,

Please see the inputs I have received internally

CC2564 can generate PCM clock of up to 4.096MHz. Please see from the datasheet:

0 Ronie Oh over 9 years ago in reply to Sundeep Javvaji

TI__Expert 3145 points

Sundeep,

The point was not how much CC2564 generated PCM clock, but how much CC2564 could generate PCM clock in stable.

Because, if the A2DP source file is made by 44.1kHz with 64 bit clock, PCM clock should be 2.822Mhz.

The customer's DAC use PCM clock as their master clock source so it is always generated over 2.8Mhz.

Thanks,

Ronie

0 Miguel over 9 years ago in reply to Ronie Oh

TI__Mastermind 23565 points

Ronie,,

Unfortunately there is no way to remove the jitter on the PCM clock. This is a known limitation. But if you use a high PCM CLK frequency and use the internal PLL on the Codec I believe you should be fine.

~Miguel

Bluetooth®︎

Bluetooth forum

CC2564 PCM clock jitter issue