SLOA159 says:
The device does not send (on pin 13) any interrupt requests on certain condition. The chip can go to a
state in which the sending of additional interrupts during RX or TX is stopped. This happens when the
Stop condition is exactly aligned with the byte boundary on TX data.
The workaround should be:
The loading and reading of the FIFO should be coded in such a way, that the Stop condition does not fall
directly on the TX byte boundary.
What is meant with "stop condition". Is it the stop condition of eg. the SPI interface (rising edge of the slave select signal) ?
What is meant with "TX byte boundary" ?
How can this be done practically ? Can you show me the part of the sample code ( out of SLOC250 ) where this is done in practice ?
Thank you...