Hi Ti employee,
I'm working on a project demands TRF7960A to read and write a ISO15693 tag(Tag-it). I have experenced on
using TRF7970A , so I migrated my TRF7970A code to TRF7960A. However, it works not quite well. I downloaded
the example code of TRF796x(sloc251.zip) and find some issues need your help.
1st) SpiReadSingle must send 0x00 when read data from TRF7960A.
void SpiReadSingle(u08_t *pbuf, u08_t number)
{
SLAVE_SELECT_LOW; // Start SPI Mode
while(number > 0)
{
// Address/Command Word Bit Distribution
*pbuf = (0x40 | *pbuf); // address, read, single
*pbuf = (0x5f & *pbuf); // register address
while (!(IFG2 & UCB0TXIFG)) // USCI_B0 TX buffer ready?
{
}
UCB0TXBUF = *pbuf; // Previous data to TX, RX
while(UCB0STAT & UCBUSY)
{
}
temp=UCB0RXBUF;
UCB0CTL0 &= ~UCCKPH;
while (!(IFG2 & UCB0TXIFG)) // USCI_B0 TX buffer ready?
{
}
UCB0TXBUF = 0x00; // Receive initiated by a dummy TX write???
// UCB0TXBUF must be assigned with 0x00, if u give 0xAA or any other value to UCB0TXBUF. This fuction will
//failed. how to explain ?
while (!(IFG2 & UCB0RXIFG)) // USCI_B0 RX buffer ready?
{
}
*pbuf = UCB0RXBUF;
pbuf++;
number--;
UCB0CTL0 |= UCCKPH;
}
while(UCB0STAT & UCBUSY)
{
}
SLAVE_SELECT_HIGH; // Stop SPI Mode
}
2nd)
void
SpiReadCont(u08_t *pbuf, u08_t length)
{
u08_t j = 0;
SLAVE_SELECT_LOW; //Start SPI Mode
// Address/Command Word Bit Distribution
*pbuf = (0x60 | *pbuf); // address, read, continuous
*pbuf = (0x7f &*pbuf); // register address
while (!(IFG2 & UCB0TXIFG)) // USCI_B0 TX buffer ready?
{
}
UCB0TXBUF = *pbuf; // Previous data to TX, RX
while(UCB0STAT & UCBUSY)
{
}
temp = UCB0RXBUF;
UCB0CTL0 &= ~UCCKPH;
if(*pbuf != 0x6C) // execute only when IRQRead is not called
{
if (length != 0x1F)
{
for (j=0;j<2;j++)
{
while (!(IFG2 & UCB0TXIFG))// USCI_B0 TX buffer ready?
{
}
UCB0TXBUF = 0x00; // Receive initiated by a dummy TX write
while(UCB0STAT & UCBUSY)
{
}
temp = UCB0RXBUF;
}
}
}
// what's the purpose of this red code ? It's not needed in TRF7970A . It looks like when we cont read a
register except (0x0C) , we need tx extra 16 CLKs ? why ?
while(length > 0)
{
while (!(IFG2 & UCB0TXIFG))
{
}
UCB0TXBUF = 0x00; // Receive initiated by a dummy TX write
while(UCB0STAT & UCBUSY)
{
}
_NOP();
_NOP();
*pbuf = UCB0RXBUF;
pbuf++;
length--;
}
UCB0CTL0 |= UCCKPH;
while(UCB0STAT & UCBUSY)
{
}
SLAVE_SELECT_HIGH; // Stop SPI Mode
}
3rd) In P2.1 interrput service routine
else if(*irq_status == BIT6)
{ // RX flag means that EOF has been recieved
// and the number of unread bytes is in FIFOstatus regiter
if(rx_error_flag == 0x02)
{
i_reg = 0x02;
return;
}
*irq_status = FIFO_STATUS;
Trf796xReadSingle(irq_status, 1); // determine the number of bytes left in FIFO
*irq_status = (0x0F &*irq_status) + 0x01;
buf[rxtx_state] = FIFO; // write the recieved bytes to the correct place of the buffer
Trf796xReadCont(&buf[rxtx_state], *irq_status);
rxtx_state = rxtx_state +*irq_status;
*irq_status = TX_LENGTH_BYTE_2; // determine if there are broken bytes
Trf796xReadCont(irq_status, 1);
if((*irq_status & BIT0) == BIT0)
{
*irq_status = (*irq_status >> 1) & 0x07; // mask the first 5 bits-------I know
*irq_status = 8 -*irq_status; // what's the meaning?
buf[rxtx_state - 1] &= 0xFF << *irq_status; // what's the meaning?
}
// I can't understang why we need to check value in register TX_LENGTH_BYTE_2 ,espasially in this RX service branch.
//In my brain, this register works only in TX process , for example when send REQA ,because this cmd is
a short frame.
#if DBG
UartPutChar('E');
#endif
Trf796xReset(); // reset the FIFO after last byte has been read out
i_reg = 0xFF; // signal to the recieve funnction that this are the last bytes
}
else if(*irq_status == 0x60)
{ // RX active and 9 bytes allready in FIFO
i_reg = 0x01;
buf[rxtx_state] = FIFO;
Trf796xReadCont(&buf[rxtx_state], 9); // read 9 bytes from FIFO
rxtx_state = rxtx_state + 9;
#if DBG
UartPutChar('F');
#endif
if(IRQ_PORT & IRQ_PIN) // if IRQ pin high
{
Trf796xReadIrqStatus(irq_status);
IRQ_CLR;
if(*irq_status == 0x40) // end of recieve
{
*irq_status = FIFO_STATUS;
Trf796xReadSingle(irq_status, 1); // determine the number of bytes left in FIFO
*irq_status = 0x0F & (*irq_status + 0x01);
buf[rxtx_state] = FIFO; // write the recieved bytes to the correct place of the buffer
Trf796xReadCont(&buf[rxtx_state], *irq_status);
rxtx_state = rxtx_state +*irq_status;
*irq_status = TX_LENGTH_BYTE_2; // determine if there are broken bytes
Trf796xReadSingle(irq_status, 1); // determine the number of bits
if((*irq_status & BIT0) == BIT0)
{
*irq_status = (*irq_status >> 1) & 0x07; // mask the first 5 bits
*irq_status = 8 -*irq_status;
buf[rxtx_state - 1] &= 0xFF << *irq_status;
}
// the same doubt....
#if DBG
UartPutChar('E');
#endif
i_reg = 0xFF; // signal to the recieve funnction that this are the last bytes
Trf796xReset(); // reset the FIFO after last byte has been read out
}
else if(*irq_status == 0x50) // end of recieve and error
{
i_reg = 0x02;
#if DBG
UartPutChar('x');
#endif
}
}
else
{
Trf796xReadIrqStatus(irq_status);
if(irq_status[0] == 0x00)
{
i_reg = 0xFF;
}
}
}
Thanks .
B&R
SeaFesse.
PS: How to edit code in the post . I find it's not a easy work to alignment. ^_^