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Non-expected rx bytes while host writing - what do they mean

Is there some information to gather from the MISO line while the host is writing? The reason I ask is I have two failing modules: one is my custom pcb and the other is a cc3000boost board. They both fail exactly the same way:

1. They get no response from first SPI message (i.e. irq never asserts) AND

2. During the first write they return the same unexpected data on the MISO line (the data in parentheses):

W:01(02) 00(04) 05(08) 00(10)
W:00(20) 01(40) 00(80) 40(80) 01(20) 00(81)

The same host gets the expected pattern on MISO when I use a non-failing wifi module:

W:01(02) 00(00) 05(ff) 00(00)
W:00(00) 01(00) 00(00) 40(00) 01(00) 00(00)

Since those unexpected bytes are consistent when they are not expected, they must mean something. What do they mean?

Roger