Hello,
I've ported the CC3100 SDK v0.5.2 driver to the Freescale Kinetis MK20. A few details about the setup:
- MK20DX256VLL7
- SPI interface
- CC3100BOOST Rev 3.3
- No RTOS
The clock polarity and phase are in mode 0. I have the nHib pin pulled up and wait until the IRQ line goes high. 75 uS later I set the CS low and start the first transmission from sl_WlanSetMode(ROLE_STA).
I see a 4 byte sync pattern (0x21 0x43 0x34 0x12) follow by another 4 byte sequence (opcode?) then a 24 byte sequence (payload?). The CS line goes high in between, but the datasheet indicated that was optional. The issue is that I never see the IRQ line go low after the transmit finishes. Where should I be looking for issues? I've attached an oscilloscope trace. Line1-Data In Line2-CLK Line3-IRQ Line 4-CS
The wiki http://processors.wiki.ti.com/index.php/CC31xx_SPI_Host_Interface#Initialization_flow indicates a different sync sequence. Did I miss a flag when I set up user.h?
Thanks!