I set up the DMA to transfer 48bytes of data, that part works well. However when I set up the interrupt, I discovered the interrupt flag in UDMA:REQDONE SSI0_TX is set, the moment SSI0:DMACR TXDMAE is set. This results in the interrupt vector being called the moment SSI0:DMACR TXDMAE is set.
On pg 1487 of the Manual it says:
"To enable uDMA operation for the transmit channel, set the [SSI:DMACR TXDMAE] register bit. If the UDMA is enabled and appropriate bits are cleared in the DMA Done Mask register, the uDMA controller triggers an interrupt when a transfer completes.
Which does not occur because, when you "enable uDMA operation" via SSI0:DMACR TXDMAE the interrupt is triggered immediately, prior to the transfer. As long as SSI0:DMACR TXDMAE is set the UDMA:REQDONE SSI0_TX flag can not be cleared. The manual goes on to say:
"The interrupt occurs on the SSI interrupt vector. If interrupts are used for SSI operation and the uDMA is enabled, the SSI interrupt handler must be designed to handle the uDMA completion interrupt. The status of TX and RX DMA done interrupts can be read from the channel request done register (UDMA:REQDONE). For clearing the TX and RX DMA done interrupts, the corresponding bits in the UDMA:REQDONE register must be 1."
However as mentioned above it is not possible to clear the TX DMA done register as long as the SSI module is set for DMA operation. A bit of a catch 22 it seems.
Has anyone come up with a work around for this that would allow "the uDMA controller to trigger an interrupt when the transfer completes"?