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Issue: 0 bytes in FIFO Status Control Register

Hey Everyone,

A few customers have been reporting rare and very intermittent issues where sometimes the TRF7970 was reporting 0 bytes in the FIFO Status Control Register, upon and Receive Complete IRQ.  This most commonly presents itself during a 15693 Inventory command, by a return of 0 bytes in the FIFO Status Control Register (0x1C).  Until now, they only fix customers have been reporting is to fully power cycle the part.  

We recently got our hands on some of these known "bad" parts and have been able to re-create this issue.  We're still doing some final testing and we'll be officially adding this to the Errata soon.  

Issue:

Upon power-up, there appears to be random values loaded into the NFC Target Detection Level Register (0x18). The default value for this register should be 0x00.  When this register is loaded with random values, it sometimes (depending on the value) interferes with the TRF7970A's reader functionality. 

NFC Target Detection Level Register (0x18) being read upon power-up.  Showing Random Values:  

  

NFC Target Detection Level Register (0x18) being read upon power-up.  Showing Correct Value (0x00):

Work Around:

Clear the NFC Target Detection Level Register (0x18) upon power-up by writing a 0x00.

 

We've tested this on TRF7970's that were currently in this state or returning 0 bytes in the FIFO Status Register, and were able to get the to operate correctly with out having to power cycle.  

I recommend making this small modification to your firmware at power-up initialization to avoid and fix this issue.

          unsigned char command[2];

          command[0] = NFCTargetLevel;
          command[1] = 0x00;
          WriteSingle(command, 2);

Thanks,

JD

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6 Replies

  • J.D.
    A few customers have been reporting rare and very intermittent issues where sometimes the TRF7970 was reporting 0 bytes in the FIFO Status Control Register, upon and Receive Complete IRQ.

    I also discovered this problem on my PLC project(passing PLC connection parameters ),but I found it was

    noise generated by the switching power supply  caused this issue. So I add the following code to avoid unexpect

    code exectution. I didn't  have a better way to solve this problem at that time. :(

     

    Beside , I found all of TRF796x(7960A/7962A/7963A)have a  IRQ signal lost  issue when  the return bytes  is  execatly a mutilple of 9 .   so , the fixed code comes

    http://e2e.ti.com/support/low_power_rf/f/667/p/309883/1080215.aspx#1080215

    note: The waring level of the FIFO in receive progess is 9 bytes .

    Hope this post  can help some people.

  • In reply to SeaFesse:

    thanks JD

    BR-

    Josh

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  • Sirs,
    The issue seems to explain my problem. Can I ask some more?

     

    Q1. 
    When the FIFO Status Control Register is updated?

    • On every RX byte ? 
    • Or, when the IRQ(pin13) asserts?
      From Datasheet>  The end of the receive operation is signaled to the external system (MCU) by sending an interrupt request (pin 13 IRQ). If the receive data packet is longer than 96 bytes, an interrupt is sent to the MCU when the received data occupies 75% of the FIFO capacity to signal that the data should be removed
      from the FIFO.

    Q2.
    Can I ask a response to SeaFesse on Mar 08 2014 08:26 AM in this thread ? My points are the followings:

    Q2-1.  The code is trying to reset the IC frequently so it would be good for an unexpected register change. But do you concern any side effects?

    Q2-2.  Trf797xReset() = the Reset(0x0F) command ~~~ this would be a new discussion. Do TI agree to issue the command as a part of the workaround?

  • In reply to Hideaki Nambu:

    Hey Hideaki,

    Hideaki Nambu

    Q1. 
    When the FIFO Status Control Register is updated?

    • On every RX byte ? 
    • Or, when the IRQ(pin13) asserts?

    I'm not sure exactly, but I would assume it would affect every RX byte.  We saw the issue when the IRQ asserts, and we read the FIFO Status register.

    Hideaki Nambu

    Q2.
    Can I ask to a response to SeaFesse on Mar 08 2014 08:26 AM in this thread ? My points are the followings:

    Q2-1.  The code is trying to reset the IC frequently so it would be good for an unexpected register change. But do you concern any side effects?

    Q2-2.  Trf797xReset() = the Reset(0x0F) command ~~~ this would be a new discussion. Do TI agree to issue the command as a part of the workaround?

     

    Their shouldn't be any side effects from resetting the TRF.  Noise on the VCC lines, as SeaFesse mentioned, could cause issues of course.  

    The Reset (0x0F) commands, is to reset the FIFO.  It just clears the FIFO out.

    Hope this helps,

    JD 

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  • In reply to John Crutchfield:

    JD,

    I appreciate your response. But the power-up value of the register 0x18 was 0x00. I'm sorry but let me make a new post about the FIFO Status Register behavior.

      "TRF7970A: Triggers to change FIFO Status Register (0x1C) value on RF receive."

     

  • In reply to Hideaki Nambu:

    Sounds good, Hideaki.

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