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TRF7970A: tSTE,LAG = 200 ns, and the maximum ?

Part Number: TRF7970A

Hello,

Is the titled parameter has a maximum limit ?

As a background, my customer expects {start, 83, stop}  (start, 80, stop}  {start, 4F, 40, stop} on SPI w/SS.

The results were sometimes {start, 83, stop}  (start, 80, stop}  {start, 4F, 00, stop}. That would be a no response from the TRF7970A.

In fail case, a tSTE,LAG delay was found like {start, 83, stop}  (start, 80, (tSTE,LAG=50usec), stop}  {start, 4F, 00, stop}.

My customer asked whether the (tSTE,LAG=51usec) explains the no response or not. Like, tSTE,LAG actually has a maximum limit.

  • Hello Hideaki,

    I did a quick test on this situation. I do not thinking the SS low time (tSTE,LAG) is the root cause. Rather, I believe they are trying to read the register too quickly after the Soft Reset/Idle process.

    Please ask them to add a 1ms delay after the Idle command which will give the TRF7970A additional time to finish processing the Soft Reset command before reading a register.

    When I tested this use case, without the delay the 50mSec time for tSTE,LAG created a 0x00 response from the read of the RSSI register, but with the 1ms delay which is recommended and done in our example firmware, the expected 0x40 response was received from the read of the RSSI register whether tSTE,LAG was 1 us or 50 us.
  • Ralph,
    I appreciate your tests and inputs. Give me a week to report you.
    By the way, is the 1msec recommendation or mandatory ?

  • Hello Hideaki,

    At this time, it is a recommendation. It isn't mandatory from our experiences, but we have seen that it can help improve performance and avoid issues in some cases and/or systems. There are applications which need not do this and still function fine however, so I wouldn't call it 'mandatory'.
  • Ralph,
    Is it possible to give the followings ?
    Honestly "definitions" would be welcomed, but I would like to talk to my customer if you could tell "recommendations". Please add margins.

    * tSTE,LAG (max)
    * tSTE,LAG (min)
    * The time between the Soft Reset and Idle (max)
    * The time between the Soft Reset and Idle (min) // This would be answered by the DS. = tSTE,LAG + tSTE,DIS + tSTE_LEAD = 700ns.
  • Hello Hideaki,

    I submitted an inquiry about if there is any spec data for the tSTE,LAG min/max.

    For the time between Soft Reset and Idle, there is no maximum as these are standalone direct commands. The minimum I would agree is based on the SPI timing specs, and no added time needs to be included between them.
  • Hello,
    If it is not easy to 'define' the tSTE,LAG min/max, do you agree to assume the 'tSTE,LAG max' as 2usec or 20usec ? It is necessary to tell a value. A very large margin would be accepted. x10 or x100 this case.

  • Hello,
    We are waiting for your input still now.
    A safe value is highly appreciated.
  • Hello Hideaki,

    There is no spec data available for the min/max of this timing. I cannot recommend min/max values without any data to back them up.

    However, I can say that in our firmware examples, commonly the tSTE,LAG time is 700-2000 ns, and that has never had issues so those values are in a safe range.

  • Ralph,
    I appreciate your cooperation. I will talk to my customer.