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TRF7964A: NTAG21x Modulation Mode Option

Part Number: TRF7964A
Other Parts Discussed in Thread: TRF7970A

Sir or Madam,

I am using a TRF7964a to access NXP NTAG21x tags over a short communication range (<10 mm).  At the end of the user memory there are four configuration pages (CFG0. CFG1, PWD and PACK).  Bit 2 of byte 0 of CFG0 (STRG_MOD_EN) enables or disables "strong modulation mode".  Outside of the datasheet for this part I could find no further references to"strong modulation mode".  It seems logical to me to enable this mode to improve communication reliability.


Does anyone else have information about this option?


Thanks in advance for your help.

Al Otis, Jr

  • Hello Alton,

    That needs to be a question directed to NXP regarding what Strong Modulation means. If you get clarity on that and want to know how it would impact the TRF7964A, then provide those details and we can comment on our end.

    For what it's worth, I've worked with many NTAG's over the years and had no issues communicating with them.
  • Ralph,


    Thank you for your prompt reply.  I have submitted a support request to NXP asking for details about the "strong modulation mode".  I will share their response whenever it arrives.

    While we are waiting I would like to ask one more question about the TRF7964A.  The "NFC Forum Type 2 Tag Platform Operations with the TRF7970A" power point presentation, which you recommended earlier, was very helpful and I am ready to dive into coding the interface.  Due to resource limitations in the product I am developing I am not able to run the NFC communication task via direct SPI and/or IRQ interrupts.  Instead the operations must be performed in a time sliced manner at an elevated priority level with 10 ms slices.  I have created a timeline drawing showing how the firmware and tag will be serviced.  Please confirm that this type of operation is acceptable.  The SPI clock frequency is 2.5 MHz.  Access time is not critical for this application.


    Best regards,

    Al

  • Ralph,

    Drawing is below.  I could not find a way to attach it as a file.

  • Hello Alton,

    While I haven't tried such an application, I think that would work fine from what I know of the device behavior. The key is that you do handle the TX Complete and FIFO clear before breaking away for 10 ms. The only possible issue you could run into in my mind would be if you read out more than 127 bytes of data from the tag and filled the FIFO, but that isn't likely to happen with NTAG21x tags so I think you should be okay from all accounts. Well done.
  • Ralph,

    Thank you for confirming that the timeline is OK.  There are multiple levels of interrupt driven tasks enabled in the system but only the 10 ms timer is always active.  However your point regarding FIFO clearing immediately after the EOTX IRQ is important.  I can solve this by allowing the IRQ signal to generate a high priority interrupt, read the interrupt status and, if EOTX, clear the FIFO.  This only takes about 25 us and would guarantee the FIFO is clear before the tag reply commences.  FYI:  I am using an ARM Cortex M4 MCU with an 80 MHz instruction execution clock.

    I will mark this support request as resolved and will open a new request when and if NXP tells me the story of "strong modulation mode"`.

    Best regards,

    Al