TRF7970A: Start Up doubt

Zhe Ming Zhuang65

Part Number: TRF7970A

Hi All:

I have some questions needed to be checked.

1. Does following figure means the first time power on ?

2. After power on, if implement EN reset and EN lead than SS about 1ms (Nevertheless SPI have been set at the first power on).

Dose there have some risk due to violation of Figure's rule?

** MOSI/MISO/CLK are directly connected to MCU, 7970 SS is connected through some logic gate to MCU.

3. Does there has any constraint for EN pin (Rising time, falling time etc..) ?

Thanks !

over 5 years ago

0 Ralph Jacobi over 5 years ago

TI__Guru*** 128095 points

Hello,

1) Yes.

2) Please see response here: e2e.ti.com/.../2652898

3) There isn't a constraint but just keep in mind that any I/O isn't viewed as high by the device until it exceeds the voltage input threshold levels as highlighted in the datasheet Section 5.3.

0 Zhe Ming Zhuang65 over 5 years ago in reply to Ralph Jacobi

Prodigy 140 points

Hi Ralph:

Thanks for your reply. I still have doubt that if VEN operate between VIL and VIH for a long time, does it have any risk for TRF7970 operation ?

As datasheet Section 5.3 shows

Thanks !

0 Ralph Jacobi over 5 years ago in reply to Zhe Ming Zhuang65

TI__Guru*** 128095 points

Hello Zhe Ming,

We have no specifications for such an occurrence as it is not considered proper system behavior to have the EN stuck between those levels aside from a slower than normal transition from low to high or vice versa. I would say if EN is held between VIL and VIH for longer than is a reasonable maximum transition time for a GPIO on a normal MCU, then we would consider that undefined behavior and cannot guarantee proper device operation.

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TRF7970A: Start Up doubt