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[CC2430] Implementing a watch dog timer in ZStack-1.4.3-1.2.1 in power saving mode

Other Parts Discussed in Thread: CC2430, Z-STACK, CC2530

I am having some issues when I implement a watch dog timer in my application on top of ZStack-1.4.3-1.2.1 in CC2430 when I enable power saving.

To give a brief overview on how i implement my algorithm, during the application's initialization (i.e SampleApp_Init) phase i created a periodic timer event using osal_start_timerEx that will fire every 750ms. After doing so I call the fundtion WatchdogTimerEnable setting it to the maximum setting of 1second.

 

I expect that before the watch dog timer expires my periodic event will first be triggered. And when that event is triggered it will just reset the watch dog timer and restart the periodic timer once again. This sound simple and should work properly. I have confirm this working when i disabled power saving. However, when power saving is enabled I can see that the device will be detected by the coordinator but after sometime it will just reset and loops this way forever.

I would then like to seek any advice from those who have implemented a watch dog timer on their application on top of Zstack-1.4.3-1.2.1 on how you are able to prevent the watch dog from preventing to reset the system on a non-fault scenario.

 

Cheers,

Grant

 

  • What Power Mode are you setting the device to in the CC2430?

    Please note that if you are in PM3, none of the clocks in the device will be enabled.  This is indicated in Table 38 in the CC2430 Datasheet available on the CC2430 Product Folder.

  • I'm setting it at PM3..but in the same specification is it also mentioned "13.13.3 Watchdog and Power Modes, In the two lowest power modes, PM2 and PM3, the watchdog is disabled and reset."

    In this case should I not worry about the watchdog timer here as it is disabled during sleep? 

    Are there extra steps that are needed when waking up for the watchdog timer (other than the periodic watchdog clear timer)?

     

  • Grant said:

    I'm setting it at PM3..but in the same specification is it also mentioned "13.13.3 Watchdog and Power Modes, In the two lowest power modes, PM2 and PM3, the watchdog is disabled and reset."

    In this case should I not worry about the watchdog timer here as it is disabled during sleep? 

    To my knowledge, implementing what is indicated in Section 13.13.3 of the CC2430 datasheet should be sufficient.  As this section indicates, when the device is in PM2 or PM3, the watchdog timer is not running.  However, it is return to the same state as it was when going from a PM0 or PM1 state to a PM2 or PM3 state, but start counting from zero.

     

    Grant said:

    Are there extra steps that are needed when waking up for the watchdog timer (other than the periodic watchdog clear timer)?

    Not that I am aware of.

  • If that is the case, has it ever been tried to enable the wathcdog timer with the ZStack-1.43-1.2.1 and have POWER_SAVING enabled?

    If so, is there a sample application to show how it is done?

    I have reconfigured my algorithm and placed the code to enable and clear the watchdog timer in osal_start_system.

    Here's my modified osal_start_system:

     

    void osal_start_system( void )
    {
    #if !defined ( ZBIT )
      for(;;)  // Forever Loop
    #endif
      {
       uint8 idx = 0;

       // Enable the watchdog timer before entering the main processing loop
      WatchDogEnable(WDTIMX);   

        Hal_ProcessPoll();  // This replaces MT_SerialPoll() and osal_check_timer().   

        do {
          if (tasksEvents[idx])  // Task is highest priority that is ready.
          {
            break;
          }
        } while (++idx < tasksCnt);

        if (idx < tasksCnt)
        {
          uint16 events;
          halIntState_t intState;

          HAL_ENTER_CRITICAL_SECTION(intState);
          events = tasksEvents[idx];
          tasksEvents[idx] = 0;  // Clear the Events for this task.
          HAL_EXIT_CRITICAL_SECTION(intState);

          events = (tasksArr[idx])( idx, events );
          
         // Reset the watchdog timer after every event processed
          WatchDogEnable(WDTIMX);   
         

          HAL_ENTER_CRITICAL_SECTION(intState);
          tasksEvents[idx] |= events;  // Add back unprocessed events to the current task.
          HAL_EXIT_CRITICAL_SECTION(intState);
        }
    #if defined( POWER_SAVING )
        else  // Complete pass through all task events with no activity?
        {
        
       // Reset the watchdog timer before going to sleep
       WatchDogEnable(WDTIMX);   

       osal_pwrmgr_powerconserve();  // Put the processor/system into sleep

       // Reset the watchdog timer after waking up from sleep
       WatchDogEnable(WDTIMX);   
        }
    #endif
        }
    }

     

  • Grant said:

    If that is the case, has it ever been tried to enable the wathcdog timer with the ZStack-1.43-1.2.1 and have POWER_SAVING enabled?

    I'm not personally aware, but isn't to say it hasn't been done.  Based on the sample code you provided, it looks reasonable.

    One thing you can add to verify if the watchdog timer is actually resetting the device is to add some checks early on in your application code to read the SLEEP Mode Control register.  Bits[4:3] provide status bits which indicate the cause of the last reset.  If the SLEEP[4:3] = 10b, it indicates a watchdog timer reset.

  • Grant,

    I'm curious. Are you still setting a timer (osal_start_timerEx) in your AppInit with your modified osal_start_system? Or are you just effectively configuring and clearing the Watchdog with your 2 calls to WatchDogEnable in your osal_start_system?

    Thanks!

  • Thanks !  Grant

       I have tried  your solution to the watchdog, it works also on the Z-stack Zstack-cc2530-2.4.0-1.40.

       Even in the PM1 state,  though the 32.768KHZ oscillator is on,  cc2530 seems staying in PM1 longer 

       than 1s without reset.   For the init&joining stages, these two phase is time-critical, occasionally 1s is

       not enough, the cc2530 resets repeatedly at 1s interval.