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【CC1200】For Diversity

Other Parts Discussed in Thread: CC1200

Hi

For the transmission operation in the case of using the diversity of the CC1200.

Storing an antenna selected by the diversity.

Data(ACK, etc.) to be transmitted next time, is outputted from the antenna selected to the receiving immediately before.

Correct?

【Experimental result】
ACK is output in the last selected antenna.
Otherwise ANT1.

Attach the setting register value.

CC1200.txt
R:reg[0x0000] dat[0x06]   name[IOCFG3] -->PKT_SYNC_RXTX(06)
R:reg[0x0001] dat[0x26]   name[IOCFG2] -->MARC_2PIN_STATUS[0](38)
R:reg[0x0002] dat[0x30]   name[IOCFG1] -->HIGHZ(48)
R:reg[0x0003] dat[0x24]   name[IOCFG0] -->ANTENNA_SELECT(36)
R:reg[0x0004] dat[0x90]   name[SYNC3]
R:reg[0x0005] dat[0x4e]   name[SYNC2]
R:reg[0x0006] dat[0x90]   name[SYNC1]
R:reg[0x0007] dat[0x4e]   name[SYNC0]
R:reg[0x0008] dat[0x48]   name[SYNC_CFG1]
R:reg[0x0009] dat[0x2a]   name[SYNC_CFG0]
R:reg[0x000a] dat[0x48]   name[DEVIATION_M]
R:reg[0x000b] dat[0x0c]   name[MODCFG_DEV_E]
R:reg[0x000c] dat[0x4b]   name[DCFILT_CFG]
R:reg[0x000d] dat[0x31]   name[PREAMBLE_CFG1]
R:reg[0x000e] dat[0x9a]   name[PREAMBLE_CFG0]
R:reg[0x000f] dat[0xd8]   name[IQIC]
R:reg[0x0010] dat[0x07]   name[CHAN_BW]
R:reg[0x0011] dat[0x42]   name[MDMCFG1]
R:reg[0x0012] dat[0x05]   name[MDMCFG0]
R:reg[0x0013] dat[0xa4]   name[SYMBOL_RATE2]
R:reg[0x0014] dat[0x7a]   name[SYMBOL_RATE1]
R:reg[0x0015] dat[0xe1]   name[SYMBOL_RATE0]
R:reg[0x0016] dat[0x2d]   name[AGC_REF]
R:reg[0x0017] dat[0xc0]   name[AGC_CS_THR]
R:reg[0x0018] dat[0xd4]   name[AGC_GAIN_ADJUST]
R:reg[0x0019] dat[0xb1]   name[AGC_CFG3]
R:reg[0x001a] dat[0x20]   name[AGC_CFG2]
R:reg[0x001b] dat[0x52]   name[AGC_CFG1]
R:reg[0x001c] dat[0xc0]   name[AGC_CFG0]
R:reg[0x001d] dat[0x05]   name[FIFO_CFG]
R:reg[0x001e] dat[0x00]   name[DEV_ADDR]
R:reg[0x001f] dat[0x0b]   name[SETTLING_CFG]
R:reg[0x0020] dat[0x12]   name[FS_CFG]
R:reg[0x0021] dat[0x08]   name[WOR_CFG1]
R:reg[0x0022] dat[0x21]   name[WOR_CFG0]
R:reg[0x0023] dat[0x00]   name[WOR_EVENT0_MSB]
R:reg[0x0024] dat[0x00]   name[WOR_EVENT0_LSB]
R:reg[0x0025] dat[0x00]   name[RXDCM_TIME]
R:reg[0x0026] dat[0x2c]   name[PKT_CFG2]
R:reg[0x0027] dat[0x45]   name[PKT_CFG1]
R:reg[0x0028] dat[0x40]   name[PKT_CFG0]
R:reg[0x0029] dat[0x3f]   name[RFEND_CFG1]
R:reg[0x002a] dat[0x35]   name[RFEND_CFG0]
R:reg[0x002b] dat[0x7f]   name[PA_CFG1]
R:reg[0x002c] dat[0x56]   name[PA_CFG0]
R:reg[0x002d] dat[0x0f]   name[ASK_CFG]
R:reg[0x002e] dat[0x00]   name[PKT_LEN]
R:reg[0x2f00] dat[0x1c]   name[IF_MIX_CFG]
R:reg[0x2f01] dat[0x20]   name[FREQOFF_CFG]
R:reg[0x2f02] dat[0x03]   name[TOC_CFG]
R:reg[0x2f03] dat[0x00]   name[MARC_SPARE]
R:reg[0x2f04] dat[0x00]   name[ECG_CFG]
R:reg[0x2f05] dat[0x02]   name[MDMCFG2]
R:reg[0x2f06] dat[0x01]   name[EXT_CTRL]
R:reg[0x2f07] dat[0x00]   name[RCCAL_FINE]
R:reg[0x2f08] dat[0x00]   name[RCCAL_COARSE]
R:reg[0x2f09] dat[0x00]   name[RCCAL_OFFSET]
R:reg[0x2f0a] dat[0x00]   name[FREQOFF1]
R:reg[0x2f0b] dat[0x00]   name[FREQOFF0]
R:reg[0x2f0c] dat[0x5c]   name[FREQ2]
R:reg[0x2f0d] dat[0x9c]   name[FREQ1]
R:reg[0x2f0e] dat[0x29]   name[FREQ0]
R:reg[0x2f0f] dat[0x02]   name[IF_ADC2]
R:reg[0x2f10] dat[0xee]   name[IF_ADC1]
R:reg[0x2f11] dat[0x10]   name[IF_ADC0]
R:reg[0x2f12] dat[0x04]   name[FS_DIG1]
R:reg[0x2f13] dat[0x55]   name[FS_DIG0]
R:reg[0x2f14] dat[0x00]   name[FS_CAL3]
R:reg[0x2f15] dat[0x20]   name[FS_CAL2]
R:reg[0x2f16] dat[0x40]   name[FS_CAL1]
R:reg[0x2f17] dat[0x0e]   name[FS_CAL0]
R:reg[0x2f18] dat[0x15]   name[FS_CHP]
R:reg[0x2f19] dat[0x03]   name[FS_DIVTWO]
R:reg[0x2f1a] dat[0x00]   name[FS_DSM1]
R:reg[0x2f1b] dat[0x33]   name[FS_DSM0]
R:reg[0x2f1c] dat[0xff]   name[FS_DVC1]
R:reg[0x2f1d] dat[0x17]   name[FS_DVC0]
R:reg[0x2f1e] dat[0x00]   name[FS_LBI]
R:reg[0x2f1f] dat[0x00]   name[FS_PFD]
R:reg[0x2f20] dat[0x6e]   name[FS_PRE]
R:reg[0x2f21] dat[0x1c]   name[FS_REG_DIV_CML]
R:reg[0x2f22] dat[0xac]   name[FS_SPARE]
R:reg[0x2f23] dat[0x18]   name[FS_VCO4]
R:reg[0x2f24] dat[0x00]   name[FS_VCO3]
R:reg[0x2f25] dat[0x6b]   name[FS_VCO2]
R:reg[0x2f26] dat[0x9c]   name[FS_VCO1]
R:reg[0x2f27] dat[0xb5]   name[FS_VCO0]
R:reg[0x2f28] dat[0x00]   name[GBIAS6]
R:reg[0x2f29] dat[0x02]   name[GBIAS5]
R:reg[0x2f2a] dat[0x00]   name[GBIAS4]
R:reg[0x2f2b] dat[0x00]   name[GBIAS3]
R:reg[0x2f2c] dat[0x10]   name[GBIAS2]
R:reg[0x2f2d] dat[0x00]   name[GBIAS1]
R:reg[0x2f2e] dat[0x00]   name[GBIAS0]
R:reg[0x2f2f] dat[0x09]   name[IFAMP]
R:reg[0x2f30] dat[0x01]   name[LNA]
R:reg[0x2f31] dat[0x01]   name[RXMIX]
R:reg[0x2f32] dat[0x0e]   name[XOSC5]
R:reg[0x2f33] dat[0xa0]   name[XOSC4]
R:reg[0x2f34] dat[0x03]   name[XOSC3]
R:reg[0x2f35] dat[0x04]   name[XOSC2]
R:reg[0x2f36] dat[0x03]   name[XOSC1]
R:reg[0x2f37] dat[0x00]   name[XOSC0]
R:reg[0x2f38] dat[0x00]   name[ANALOG_SPARE]
R:reg[0x2f39] dat[0x00]   name[PA_CFG3]
R:reg[0x2f3f] dat[0x00]   name[IRQ0M]
R:reg[0x2f40] dat[0x80]   name[IRQ0F]
R:reg[0x2f64] dat[0x00]   name[WOR_TIME1]
R:reg[0x2f65] dat[0x00]   name[WOR_TIME0]
R:reg[0x2f66] dat[0x00]   name[WOR_CAPTURE1]
R:reg[0x2f67] dat[0x00]   name[WOR_CAPTURE0]
R:reg[0x2f68] dat[0x00]   name[BIST]
R:reg[0x2f69] dat[0x00]   name[DCFILTOFFSET_I1]
R:reg[0x2f6a] dat[0x00]   name[DCFILTOFFSET_I0]
R:reg[0x2f6b] dat[0x00]   name[DCFILTOFFSET_Q1]
R:reg[0x2f6c] dat[0x00]   name[DCFILTOFFSET_Q0]
R:reg[0x2f6d] dat[0x00]   name[IQIE_I1]
R:reg[0x2f6e] dat[0x00]   name[IQIE_I0]
R:reg[0x2f6f] dat[0x00]   name[IQIE_Q1]
R:reg[0x2f70] dat[0x00]   name[IQIE_Q0]
R:reg[0x2f71] dat[0xb6]   name[RSSI1]
R:reg[0x2f72] dat[0x43]   name[RSSI0]
R:reg[0x2f73] dat[0x41]   name[MARCSTATE]
R:reg[0x2f74] dat[0x00]   name[LQI_VAL]
R:reg[0x2f75] dat[0xff]   name[PQT_SYNC_ERR]
R:reg[0x2f76] dat[0x00]   name[DEM_STATUS]
R:reg[0x2f77] dat[0xfe]   name[FREQOFF_EST1]
R:reg[0x2f78] dat[0xf6]   name[FREQOFF_EST0]
R:reg[0x2f79] dat[0x27]   name[AGC_GAIN3]
R:reg[0x2f7a] dat[0xd1]   name[AGC_GAIN2]
R:reg[0x2f7b] dat[0x00]   name[AGC_GAIN1]
R:reg[0x2f7c] dat[0x3f]   name[AGC_GAIN0]
R:reg[0x2f7d] dat[0x00]   name[CFM_RX_DATA_OUT]
R:reg[0x2f7e] dat[0x00]   name[CFM_TX_DATA_IN]
R:reg[0x2f7f] dat[0x30]   name[ASK_SOFT_RX_DATA]
R:reg[0x2f80] dat[0x7f]   name[RNDGEN]
R:reg[0x2f81] dat[0x00]   name[MAGN2]
R:reg[0x2f82] dat[0x00]   name[MAGN1]
R:reg[0x2f83] dat[0x08]   name[MAGN0]
R:reg[0x2f84] dat[0x03]   name[ANG1]
R:reg[0x2f85] dat[0x35]   name[ANG0]
R:reg[0x2f86] dat[0x02]   name[CHFILT_I2]
R:reg[0x2f87] dat[0x00]   name[CHFILT_I1]
R:reg[0x2f88] dat[0x00]   name[CHFILT_I0]
R:reg[0x2f89] dat[0x00]   name[CHFILT_Q2]
R:reg[0x2f8a] dat[0x00]   name[CHFILT_Q1]
R:reg[0x2f8b] dat[0x00]   name[CHFILT_Q0]
R:reg[0x2f8c] dat[0x00]   name[GPIO_STATUS]
R:reg[0x2f8d] dat[0x01]   name[FSCAL_CTRL]
R:reg[0x2f8e] dat[0x00]   name[PHASE_ADJUST]
R:reg[0x2f8f] dat[0x20]   name[PARTNUMBER]
R:reg[0x2f90] dat[0x11]   name[PARTVERSION]
R:reg[0x2f91] dat[0x00]   name[SERIAL_STATUS]
R:reg[0x2f92] dat[0x11]   name[MODEM_STATUS1]
R:reg[0x2f93] dat[0x00]   name[MODEM_STATUS0]
R:reg[0x2f94] dat[0x02]   name[MARC_STATUS1]
R:reg[0x2f95] dat[0x00]   name[MARC_STATUS0]
R:reg[0x2f96] dat[0x00]   name[PA_IFAMP_TEST]
R:reg[0x2f97] dat[0x00]   name[FSRF_TEST]
R:reg[0x2f98] dat[0x00]   name[PRE_TEST]
R:reg[0x2f99] dat[0x00]   name[PRE_OVR]
R:reg[0x2f9a] dat[0x00]   name[ADC_TEST]
R:reg[0x2f9b] dat[0x0b]   name[DVC_TEST]
R:reg[0x2f9c] dat[0x40]   name[ATEST]
R:reg[0x2f9d] dat[0x00]   name[ATEST_LVDS]
R:reg[0x2f9e] dat[0x00]   name[ATEST_MODE]
R:reg[0x2f9f] dat[0x00]   name[XOSC_TEST1]
R:reg[0x2fa0] dat[0x00]   name[XOSC_TEST0]
R:reg[0x2fa1] dat[0x00]   name[AES]
R:reg[0x2fa2] dat[0x00]   name[MDM_TEST]
R:reg[0x2fd2] dat[0x00]   name[RXFIRST]
R:reg[0x2fd3] dat[0x00]   name[TXFIRST]
R:reg[0x2fd4] dat[0x00]   name[RXLAST]
R:reg[0x2fd5] dat[0x00]   name[TXLAST]
R:reg[0x2fd6] dat[0x00]   name[NUM_TXBYTES]
R:reg[0x2fd7] dat[0x00]   name[NUM_RXBYTES]
R:reg[0x2fd8] dat[0x0f]   name[FIFO_NUM_TXBYTES]
R:reg[0x2fd9] dat[0x00]   name[FIFO_NUM_RXBYTES]

Best Regards,

Kozo

  • In TX, the device will transmit ACK on the same antenna that received the last packet. This is stated in the Antenna Diversity App report (SWRA469).

    Siri

  • Dear Siri-san

    Thank you.

    However, it is fixed to ANT1.

    What are the possible causes?
    I want to know the data required to investigate the cause.

    Best Regards,

    Kozo

  • Dear Siri-san

    I'm sorry.

    Could you answer?

    Best Regards,

    Kozo

  • Hi

    In particular the antenna is different from the receiving antenna phenomenon when sending an ACK has become a problem.
    Please advice.
    Best Regards,
    Kozo
  • Hi Kozo

    I will do some testing here on my side and then come back to you as soon as I have results to share.

    BR

    Siri

  • I did a test were I used 2 CC1200 and SmartRF Studio. I used the 38.4 kbps setting and output the ANTENNAS_SELECT signal on GPIO3 and the packet PKT_SYNC_RXTX on GPIO2. I used RXOFF_MODE = TX to send an ACK and had ANT_DIV_RX_TERM_CFG = 3.

    The plots below show that the ACK packet is transmitted with the same antenna as the last packet was received on. In the first plot ANTENNA_SELECT is high for both packets received and packet sent, and in the next plot it is low for both RX and TX.

  • Dear

    Thank you.

    However, the receiving antenna that sent the ACK antenna does not match.
    Attach the SmartRF configuration file.

    Please check. I'm sorry.

    cc1200_Def_DUT_Setting.xml
    <?xml version="1.0" encoding="ISO-8859-1"?>
    <!DOCTYPE configuration SYSTEM "C:/Program Files/Texas Instruments/SmartRF Tools/SmartRF Studio 7/config/xml/configdata.dtd"[]>
    <dcpanelconfiguration>
        <Devicename>CC1200</Devicename>
        <Description>Saved configuration data</Description>
        <registersettings>
            <Register>
                <Name>AGC_CFG0</Name>
                <Value>0x80</Value>
            </Register>
            <Register>
                <Name>AGC_CFG1</Name>
                <Value>0x12</Value>
            </Register>
            <Register>
                <Name>AGC_CS_THR</Name>
                <Value>0x01</Value>
            </Register>
            <Register>
                <Name>AGC_REF</Name>
                <Value>0x2a</Value>
            </Register>
            <Register>
                <Name>CHAN_BW</Name>
                <Value>0x08</Value>
            </Register>
            <Register>
                <Name>DCFILT_CFG</Name>
                <Value>0x4b</Value>
            </Register>
            <Register>
                <Name>DEVIATION_M</Name>
                <Value>0x48</Value>
            </Register>
            <Register>
                <Name>FIFO_CFG</Name>
                <Value>0x00</Value>
            </Register>
            <Register>
                <Name>FREQ1</Name>
                <Value>0x40</Value>
            </Register>
            <Register>
                <Name>FREQ2</Name>
                <Value>0x5c</Value>
            </Register>
            <Register>
                <Name>FS_CAL0</Name>
                <Value>0x0e</Value>
            </Register>
            <Register>
                <Name>FS_CAL1</Name>
                <Value>0x40</Value>
            </Register>
            <Register>
                <Name>FS_CFG</Name>
                <Value>0x12</Value>
            </Register>
            <Register>
                <Name>FS_DIG0</Name>
                <Value>0xa5</Value>
            </Register>
            <Register>
                <Name>FS_DIG1</Name>
                <Value>0x07</Value>
            </Register>
            <Register>
                <Name>FS_DIVTWO</Name>
                <Value>0x03</Value>
            </Register>
            <Register>
                <Name>FS_DSM0</Name>
                <Value>0x33</Value>
            </Register>
            <Register>
                <Name>FS_DVC0</Name>
                <Value>0x17</Value>
            </Register>
            <Register>
                <Name>FS_PFD</Name>
                <Value>0x00</Value>
            </Register>
            <Register>
                <Name>FS_PRE</Name>
                <Value>0x6e</Value>
            </Register>
            <Register>
                <Name>FS_REG_DIV_CML</Name>
                <Value>0x1c</Value>
            </Register>
            <Register>
                <Name>FS_SPARE</Name>
                <Value>0xac</Value>
            </Register>
            <Register>
                <Name>FS_VCO0</Name>
                <Value>0xb5</Value>
            </Register>
            <Register>
                <Name>IFAMP</Name>
                <Value>0x09</Value>
            </Register>
            <Register>
                <Name>IF_ADC0</Name>
                <Value>0x10</Value>
            </Register>
            <Register>
                <Name>IF_ADC1</Name>
                <Value>0xee</Value>
            </Register>
            <Register>
                <Name>IF_MIX_CFG</Name>
                <Value>0x1c</Value>
            </Register>
            <Register>
                <Name>IOCFG0</Name>
                <Value>0x24</Value>
            </Register>
            <Register>
                <Name>IOCFG2</Name>
                <Value>0x06</Value>
            </Register>
            <Register>
                <Name>IQIC</Name>
                <Value>0xd8</Value>
            </Register>
            <Register>
                <Name>MDMCFG0</Name>
                <Value>0x05</Value>
            </Register>
            <Register>
                <Name>MDMCFG1</Name>
                <Value>0x42</Value>
            </Register>
            <Register>
                <Name>MDMCFG2</Name>
                <Value>0x02</Value>
            </Register>
            <Register>
                <Name>MODCFG_DEV_E</Name>
                <Value>0x0c</Value>
            </Register>
            <Register>
                <Name>MODEM_STATUS1</Name>
                <Value>0x10</Value>
            </Register>
            <Register>
                <Name>PARTNUMBER</Name>
                <Value>0x20</Value>
            </Register>
            <Register>
                <Name>PARTVERSION</Name>
                <Value>0x10</Value>
            </Register>
            <Register>
                <Name>PKT_CFG0</Name>
                <Value>0x40</Value>
            </Register>
            <Register>
                <Name>PKT_CFG1</Name>
                <Value>0x45</Value>
            </Register>
            <Register>
                <Name>PKT_CFG2</Name>
                <Value>0x2c</Value>
            </Register>
            <Register>
                <Name>PKT_LEN</Name>
                <Value>0xff</Value>
            </Register>
            <Register>
                <Name>PREAMBLE_CFG0</Name>
                <Value>0x9a</Value>
            </Register>
            <Register>
                <Name>PREAMBLE_CFG1</Name>
                <Value>0x31</Value>
            </Register>
            <Register>
                <Name>RFEND_CFG0</Name>
                <Value>0x36</Value>
            </Register>
            <Register>
                <Name>RFEND_CFG1</Name>
                <Value>0x3d</Value>
            </Register>
            <Register>
                <Name>SYMBOL_RATE0</Name>
                <Value>0xe1</Value>
            </Register>
            <Register>
                <Name>SYMBOL_RATE1</Name>
                <Value>0x7a</Value>
            </Register>
            <Register>
                <Name>SYMBOL_RATE2</Name>
                <Value>0xa4</Value>
            </Register>
            <Register>
                <Name>SYNC0</Name>
                <Value>0x4e</Value>
            </Register>
            <Register>
                <Name>SYNC1</Name>
                <Value>0x90</Value>
            </Register>
            <Register>
                <Name>SYNC2</Name>
                <Value>0x4e</Value>
            </Register>
            <Register>
                <Name>SYNC3</Name>
                <Value>0x90</Value>
            </Register>
            <Register>
                <Name>SYNC_CFG0</Name>
                <Value>0x2a</Value>
            </Register>
            <Register>
                <Name>SYNC_CFG1</Name>
                <Value>0x48</Value>
            </Register>
            <Register>
                <Name>TOC_CFG</Name>
                <Value>0x03</Value>
            </Register>
            <Register>
                <Name>XOSC1</Name>
                <Value>0x03</Value>
            </Register>
            <Register>
                <Name>XOSC5</Name>
                <Value>0x0e</Value>
            </Register>
        </registersettings>
        <dcpanel>
            <Property name="m_chkRegView" role="44">2</Property>
            <Property name="m_chkRfParameters" role="44">2</Property>
            <Property name="m_tabUserMode" role="37">1</Property>
            <Property name="m_easyModeSettings" role="33">-1</Property>
            <Property name="m_typicalSettings" role="33">-1</Property>
            <Property name="m_testFuncPanel" role="37">3</Property>
        </dcpanel>
        <rfparameters>
            <Property name="m_cmbFrontends" role="46">0</Property>
            <Property name="m_chkHGMorBYP" role="44">2</Property>
            <Property name="m_cmbEmRevs" role="46">-1</Property>
            <Property name="Xtal frequency" role="46">40.000000</Property>
        </rfparameters>
        <conttx>
            <Property name="m_rbtModulated" role="45">1</Property>
            <Property name="m_rbtUnmodulated" role="45">0</Property>
            <Property name="m_cmbDataFormat" role="46">-1</Property>
            <Property name="m_chkFreqSweep" role="44">0</Property>
            <Property name="m_chkChanSweep" role="44">0</Property>
        </conttx>
        <contrx>
            <Property name="m_cmbDataFormat" role="46">-1</Property>
            <Property name="m_chkAutoScroll" role="44">2</Property>
        </contrx>
        <packettx>
            <Property name="m_edtPacketCount" role="42">100</Property>
            <Property name="m_edtPacketCountEsy" role="42">100</Property>
            <Property name="m_edtFixedPktLength" role="42">255</Property>
            <Property name="m_edtPacketData" role="42">ce 63 09 dd 3d f5 f4 74 ab 52 22 55 06 84 0b 66 af 33 3e 49 d0 b2 56 81 f0 40 </Property>
            <Property name="m_edtAccessAddress" role="42"></Property>
            <Property name="m_chkAddSeqNbr" role="44">2</Property>
            <Property name="m_chkInfinite" role="44">0</Property>
            <Property name="m_chkInfiniteEsy" role="44">0</Property>
            <Property name="m_rbtRandom" role="45">1</Property>
            <Property name="m_rbtText" role="45">0</Property>
            <Property name="m_rbtHex" role="45">0</Property>
            <Property name="m_chkAdvanced" role="44">0</Property>
            <Property name="m_cmbLengthConfig" role="46">1</Property>
            <Property name="m_edtFixedPktLength" role="42">255</Property>
            <Property name="m_edtBitLength" role="42">0</Property>
            <Property name="m_grp802154g" role="20">1</Property>
            <Property name="m_edt802154gPktLength" role="42">30</Property>
            <Property name="m_rbt802154g2BCrc" role="45">1</Property>
            <Property name="m_rbt802154g4BCrc" role="45">0</Property>
            <Property name="m_chk802154gWhitening" role="44">2</Property>
            <Property name="m_chkFEC" role="44">0</Property>
            <Property name="m_cmbPreambleCount" role="46">12</Property>
            <Property name="m_chkAddress" role="44">0</Property>
            <Property name="m_cmbSyncMode" role="46">2</Property>
        </packettx>
        <packetview>
            <Property name="m_edtPktLength" role="42">30</Property>
            <Property name="m_lblFrmPayload" role="41">13 b6 da 79 e8 66 7b bc e8 49 66 82 49 51 15 67 06 18 05 03 27 18 1b be 42 1e </Property>
        </packetview>
        <packetrx>
            <Property name="m_edtPacketCount" role="42">100</Property>
            <Property name="m_edtPacketCountEsy" role="42">100</Property>
            <Property name="m_edtAccessAddress" role="42"></Property>
            <Property name="m_chkInfinite" role="44">2</Property>
            <Property name="m_chkInfiniteEsy" role="44">2</Property>
            <Property name="m_cmbViewFormat" role="46">0</Property>
            <Property name="m_chkSeqNbrIncluded" role="44">2</Property>
            <Property name="m_edtDumpFile" role="42"></Property>
            <Property name="m_chkAdvanced" role="44">0</Property>
            <Property name="m_chk802154gMode" role="44">2</Property>
        </packetrx>
        <commandpanel>
            <Property name="m_chkInsertLength" role="44">0</Property>
            <Property name="m_edtTxFifo" role="42"></Property>
            <Property name="m_edtRxFifo" role="42"></Property>
            <Property name="m_cmbInstrInput" role="46">-1</Property>
        </commandpanel>
        <packetRxSniffMode>
            <Property name="m_edtPreambleLength" role="42">24</Property>
            <Property name="m_edtCarrierSenseThreshold" role="42">-90</Property>
            <Property name="m_rbtRssi" role="45">1</Property>
            <Property name="m_rbtPreamble" role="45">0</Property>
        </packetRxSniffMode>
    </dcpanelconfiguration>
    

    Setting wrong?

    Expect wrong?

    Best Regards,

    Kozo

  • Dear Siri-san

    I'm sorry.

    Could you answer?

    Best Regards,

    Kozo

  • Hi Kozo
    I cannot see anything wrong with the settings. Unfortunately I do not have HW to test with right now. Can you please send a plot of the antenna signal and of packet sent and packet received and explain me what you think looks wrong? If the signal is low when a packet is received it should stay low when entering TX and if it is high when sync is found it should be high next time in TX (just like I showed you in my previous post). Are you oberving something different than that?

    Siri
  • Hi Siri

    It has been supported by SW.
    And, it has been resolved.

    Thank you.

    Best Regards,

    Kozo