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CC1101 RX channel filter Bandwidth

Mekdelawit Enna
Prodigy 100 points
Other Parts Discussed in Thread: CC1101, TEST2

HI everyone ,

i"m working on CC1101(433 Mhz) point to multipoint and mesh networks.And i want to set the slave node to receive a packet from any channel which i think is possible with channel interference and setting the receiver with maximum RX channel filter BW . With minimum channel spacing (25.39Khz) and 812 Khz receiver BW i set the slave node on channel 0x00 and it receives a packet from a master which is sending on channel 0x09.But couldn't go any further like channel 0x0A or above .I post my register setting if in case you want it and my question is how can i make a slave node receive from any channel.I don't mean @ the same time .Pls any help would be appreciated ASAP.Thank you.

WriteReg( CC1101_SYNC1 ,0xD3);  //D3
    WriteReg( CC1101_SYNC0 , 0x91);
    WriteReg(CC1101_IOCFG2,  0x06); // GDO2 output pin config.(sync send & packet send )
    WriteReg(CC1101_IOCFG1,  0x04); // GDO1 output pin config(different from 0x2E to see the status on MISO)(0x14 for CS)
    WriteReg(CC1101_IOCFG0,  0x07); // GDO0 output pin config.(Packet received w' CRC OK)
    WriteReg(CC1101_FIFOTHR,  0x47);  ///33Txfifo & 32 Rxfifo
    WriteReg(CC1101_PKTLEN,   0x3D); // Packet length(61  bytes ,1 address and 2 append status)
    WriteReg(CC1101_PKTCTRL1, 0x8E); // (0x84(8C crc auto flush) no addr chk,append status,sync word)(0x04)Packet automation control(append status enabled ,no addr chk ,sync word always accepted ,no CRC autoflush)(0x8E address check,sync word detected,crc autofush enabled)
    WriteReg(CC1101_PKTCTRL0, 0x05); // Packet automation control(CRC enabled ,variable packet length)
    WriteReg(CC1101_ADDR,     0x01); // Device address.
    WriteReg(CC1101_CHANNR,   0x00); // Channel number.
    WriteReg(CC1101_FSCTRL1,  0x06); // Freq synthesizer control.152.343 IF_FREQ
    WriteReg(CC1101_FSCTRL0,  0x00); // Freq synthesizer control.
    WriteReg(CC1101_FREQ2,    0x10); // Freq control word, high byte
    WriteReg(CC1101_FREQ1,    0xB1); // Freq control word, mid byte.
    WriteReg(CC1101_FREQ0,    0x3B); // Freq control word, low byte.
    WriteReg(CC1101_MDMCFG4,  0x06); // Modem configuration(2.4Kbaud)  812 khz channel filter BW
    WriteReg(CC1101_MDMCFG3,  0x83); // Modem configuration.(DRATE_M=131)
    WriteReg(CC1101_MDMCFG2,  0x13); // Modem configuration.(DRATE_E=6)GFSK
    WriteReg(CC1101_MDMCFG1,  0x20); // Modem configuration.22
    WriteReg(CC1101_MDMCFG0,  0x00); // Modem configuration.F8
    WriteReg(CC1101_DEVIATN,  0x15); // Modem dev (when FSK mod en)5.125khz freq. deviation
    WriteReg(CC1101_MCSM2 ,   0x07);  ///RX timeout until end of packet(0x07)
    WriteReg(CC1101_MCSM1 ,   0x33); //MainRadio Ctrl State Machine(Tx --> Rx  and RX-->IDLE ,CCA if RSSI below threshold )
    WriteReg(CC1101_MCSM0 ,   0x18); //MainRadio Ctrl State Machine(Calibrate from idle to TX and RX ,force XOSC to stay in sleep mode)(0x28 from,tx to idle)
    WriteReg(CC1101_FOCCFG,   0x16); // Freq Offset Compens. Config
    WriteReg(CC1101_BSCFG,    0x6C); //  Bit synchronization config.
    WriteReg(CC1101_AGCCTRL2, 0xC7); // AGC control.( MAGN_TARGET 42dB ,MAX_LNA_GAIN =0 ,MAX_DVGA_GAIN =0)
    WriteReg(CC1101_AGCCTRL1, 0x40); // AGC control.(absolute carrier sense threshold at MAGN_TARGET 33dB)
    WriteReg(CC1101_AGCCTRL0, 0x91); // AGC control(Always adjust gain when required)
    WriteReg(CC1101_WOREVT1,0x87); //High Byte Event0 Timeout
    WriteReg(CC1101_WOREVT0,0x6B); //Low Byte Event0 Timeout
    WriteReg(CC1101_WORCTRL,0xFB); //Wake On Radio Control
    WriteReg(CC1101_FREND1,   0xB6); // 56Front end RX configuration.
    WriteReg(CC1101_FREND0,   0x10); // Front end RX configuration.
    WriteReg(CC1101_FSCAL3,   0xE9); // Frequency synthesizer cal.
    WriteReg(CC1101_FSCAL2,   0x2A); // Frequency synthesizer cal.
    WriteReg(CC1101_FSCAL1,   0x00); // Frequency synthesizer cal.
    WriteReg(CC1101_FSCAL0,   0x1F); // Frequency synthesizer cal.
    WriteReg(CC1101_RCCTRL1,0x41); //RC Oscillator Configuration
    WriteReg(CC1101_RCCTRL0,0x00); //RC Oscillator Configuration
    WriteReg(CC1101_FSTEST,   0x59); // Frequency synthesizer cal.
    WriteReg(CC1101_PTEST, 0x7F);
    WriteReg(CC1101_AGCTEST, 0x3F);
    WriteReg(CC1101_TEST2,    0x81); // Various test settings.
    WriteReg(CC1101_TEST1,    0x35); // Various test settings.
    WriteReg(CC1101_TEST0,    0x09); // Various test settings.
    
    WriteReg(CC1101_PATABLE,    0xC0);     /// 0x0C with 433Mhz carrier freq. means 10dbm

  • 0
    TI__Guru**** 317180 points

    We looked at your settings and have a theory about why it doesn't work.

    When finding the optimal receive parameters for CC1101 the receive bandwidth is an important parameter. If you use SmartRF Studio to give the settings, you should find the predefined setting that has the RX bandwidth that is closest to what you need and then from this set the wanted datarate and deviation. In this case it's probably the IF frequency that causes a problem (FSCTRL1), the frequency you use is too low compared to the Rx bandwidth. 

  • 0 in reply to TER
    Prodigy 100 points

    Thank you TER for the reply.
            I did configure FSCTRL1 register to 1F which is 787.109 Khz and relatively very close to 812 Khz RX bandwidth.And increased the frequency deviation from 5.125 Khz to 380.859 Khz and it did bring a slight change .When master on channel 17 and slave on 0 , the slave received from the master but the Master couldn't go further like channel 18 and beyond .I used SmartRF Studio for generating the register setting.To make it clear ,my project aims at Point to Multipoint communication and the slaves set to channel 0x00 at first and they should receive a discovery message from any master on any channel which is nearby.Then after that the slave will set it's channel to the master's which the channel number will be included in the first packet sent from the master. But first the slave should receive from any channel with channel interference.This works perfect from channel 0x01 to 0x09. Could you please explain how freq deviation , data rate and IF freq are related to this and if you have any suggestion on the register settings ? Thanks in advance!!!

  • 0 in reply to Mekdelawit Enna
    TI__Mastermind 39860 points

    Start with the 500 kBaud setting in Smart RF Studio. Change modulation format to GFSK, data rate to 2.4 kBaud, deviation to 5.2 kHz and channel spacing to 25 kHz.  FSCTRL1 will then be set to 0xE. Furthermore, settings related to the AGC and some other registers will be set to fit the 812 kHz RX BW.

    In the attached powerpoint I have tried to illustrate what can be achieved when slave is set to channel 0.

    E2E figure.pptx

  • 0 in reply to Sverre
    Prodigy 100 points

    Hi Sverre ,

    I tried what u wrote on the power point ,it really helped.and i saw the channel can go up to 19.(When slave on  0x00 and master on 0x13(19) ).The frequency offset was set to 400 khz (a little less than 812 rx filter BW / 2 ).I want the maximum channel to be 30(0x1E).How can i do that pls?

  • 0 in reply to Mekdelawit Enna
    TI__Mastermind 39860 points

    Check if the attached suggestion works.

    E2E figure Rev 2.pptx

  • 0 in reply to Sverre
    Prodigy 100 points

    Thank you so much Sverre .

         I now clearly understand what u said. But i still can't use the full channel  BW. When i set the slave on 0x10 , it receives from  channel 0x1E perfectly but cudn't even receive from channel 0x0A.That means i'm not able to use the lower half.If the reason is from my register setting for the slave node please check it.I used SmartRF studio for setting the register.

                                                                                              Best Regards.

    WriteReg( CC1101_SYNC1 ,0xD3);  //D3
        WriteReg( CC1101_SYNC0 , 0x91);
        WriteReg(CC1101_IOCFG2,  0x06); // GDO2 output pin config.(sync send & packet send )
        WriteReg(CC1101_IOCFG1,  0x04); // GDO1 output pin config(different from 0x2E to see the status on MISO)(0x14 for CS)
        WriteReg(CC1101_IOCFG0,  0x07); // GDO0 output pin config.(Packet received w' CRC OK)
        WriteReg(CC1101_FIFOTHR,  0x47);  ///33Txfifo & 32 Rxfifo
        WriteReg(CC1101_PKTLEN,   0x3D); // Packet length(61  bytes ,1 address and 2 append status)
        WriteReg(CC1101_PKTCTRL1, 0x8E);
        WriteReg(CC1101_PKTCTRL0, 0x05); // Packet automation control(CRC enabled ,variable packet length)
        
        
        WriteReg(CC1101_ADDR,     0x02); // Device address.
        WriteReg(CC1101_CHANNR,   0x10); // Channel number.
        
        WriteReg(CC1101_FSCTRL1,  0x1F); // Freq synthesizer control.152.343 IF_FREQ (1F=787.109Khz)
        WriteReg(CC1101_FSCTRL0,  0x6F); // Freq synthesizer control.   //6F
        WriteReg(CC1101_FREQ2,    0x10); // Freq control word, high byte
        WriteReg(CC1101_FREQ1,    0xB1); // Freq control word, mid byte.
        WriteReg(CC1101_FREQ0,    0x3B); // Freq control word, low byte.
        WriteReg(CC1101_MDMCFG4,  0x06); // Modem configuration(2.4Kbaud)  812 khz channel filter BW   
        WriteReg(CC1101_MDMCFG3,  0x83); // Modem configuration.(DRATE_M=131)                    
        WriteReg(CC1101_MDMCFG2,  0x13); // Modem configuration.(DRATE_E=6)GFSK
        WriteReg(CC1101_MDMCFG1,  0x20); // Modem configuration.22
        WriteReg(CC1101_MDMCFG0,  0x00); // Modem configuration.F8
        WriteReg(CC1101_DEVIATN,  0x77); // Modem dev (when FSK mod en)5.125khz freq. deviation
        WriteReg(CC1101_MCSM2 ,   0x07);  ///RX timeout until end of packet(0x07)
        WriteReg(CC1101_MCSM1 ,   0x33); //MainRadio Ctrl State Machine(Tx --> Rx  and RX-->IDLE ,CCA if RSSI below threshold )
        WriteReg(CC1101_MCSM0 ,   0x18); //MainRadio Ctrl State Machine(Calibrate from idle to TX and RX ,force XOSC to stay in sleep mode)(0x28 from,tx to idle)
        WriteReg(CC1101_FOCCFG,   0x16); // Freq Offset Compens. Config
        WriteReg(CC1101_BSCFG,    0x6C); //  Bit synchronization config.
        WriteReg(CC1101_AGCCTRL2, 0x43); // AGC control.( MAGN_TARGET 42dB ,MAX_LNA_GAIN =0 ,MAX_DVGA_GAIN =0)
        WriteReg(CC1101_AGCCTRL1, 0x49); // AGC control.(absolute carrier sense threshold at MAGN_TARGET 33dB)
        WriteReg(CC1101_AGCCTRL0, 0x91); // AGC control(Always adjust gain when required)
        WriteReg(CC1101_WOREVT1,0x87); //High Byte Event0 Timeout
        WriteReg(CC1101_WOREVT0,0x6B); //Low Byte Event0 Timeout
        WriteReg(CC1101_WORCTRL,0xFB); //Wake On Radio Control
        WriteReg(CC1101_FREND1,   0xB6); // 56Front end RX configuration.
        WriteReg(CC1101_FREND0,   0x10); // Front end RX configuration.
        WriteReg(CC1101_FSCAL3,   0xE9); // Frequency synthesizer cal.
        WriteReg(CC1101_FSCAL2,   0x2A); // Frequency synthesizer cal.
        WriteReg(CC1101_FSCAL1,   0x00); // Frequency synthesizer cal.
        WriteReg(CC1101_FSCAL0,   0x1F); // Frequency synthesizer cal.
        WriteReg(CC1101_RCCTRL1,0x41); //RC Oscillator Configuration
        WriteReg(CC1101_RCCTRL0,0x00); //RC Oscillator Configuration
        WriteReg(CC1101_FSTEST,   0x59); // Frequency synthesizer cal.
        WriteReg(CC1101_PTEST, 0x7F);
        WriteReg(CC1101_AGCTEST, 0x3F);
        WriteReg(CC1101_TEST2,    0x81); // Various test settings.
        WriteReg(CC1101_TEST1,    0x35); // Various test settings.
        WriteReg(CC1101_TEST0,    0x09); // Various test settings.
        
        WriteReg(CC1101_PATABLE,    0xC0);     /// 0x0C with 433Mhz carrier freq. means 10dbm

  • 0 in reply to Mekdelawit Enna
    TI__Mastermind 39860 points

    I tried the settings below following. I was able to receive up to 100 kHz offset (4 channels) below and above sensor, which was set to channel 15. I suspect that the offset in IF frequency cannot be too large as both the logic 0 and logic 1 will be below the decision level for large negative offset or both will be above the decision level for large positive offset. 

    Things to try: 

    - longer preamble

    - enable whitening

    - set AGCCTRL0.FILTER_LENGTH to 3

    // Packet length = 255

    // Manchester enable = false

    // Sync word qualifier mode = 30/32 sync word bits detected

    // Deviation = 25.390625

    // Carrier frequency = 433.380676

    // Device address = 0

    // Base frequency = 432.999817

    // TX power = 0

    // Modulation format = GFSK

    // Modulated = true

    // CRC autoflush = false

    // Data format = Normal mode

    // Packet length mode = Variable packet length mode. Packet length configured by the first byte after sync word

    // CRC enable = true

    // Whitening = false

    // PA ramping = false

    // Data rate = 2.39897

    // RX filter BW = 812.500000

    // Address config = No address check

    // Preamble count = 8

    // Channel spacing = 25.390625

    // Channel number = 15

    // Rf settings for CC1101

    RF_SETTINGS code rfSettings = {

    0x06, // IOCFG0 GDO0 Output Pin Configuration

    0x05, // PKTCTRL0 Packet Automation Control

    0x0F, // CHANNR Channel Number

    0x10, // FREQ2 Frequency Control Word, High Byte

    0xA7, // FREQ1 Frequency Control Word, Middle Byte

    0x62, // FREQ0 Frequency Control Word, Low Byte

    0x06, // MDMCFG4 Modem Configuration

    0x83, // MDMCFG3 Modem Configuration

    0x13, // MDMCFG2 Modem Configuration

    0x40, // MDMCFG1 Modem Configuration

    0x00, // MDMCFG0 Modem Configuration

    0x40, // DEVIATN Modem Deviation Setting

    0x18, // MCSM0 Main Radio Control State Machine Configuration

    0x1D, // FOCCFG Frequency Offset Compensation Configuration

    0x1C, // BSCFG Bit Synchronization Configuration

    0xC7, // AGCCTRL2 AGC Control

    0x00, // AGCCTRL1 AGC Control

    0xB0, // AGCCTRL0 AGC Control

    0xB6, // FREND1 Front End RX Configuration

    0xE9, // FSCAL3 Frequency Synthesizer Calibration

    0x2A, // FSCAL2 Frequency Synthesizer Calibration

    0x00, // FSCAL1 Frequency Synthesizer Calibration

    0x1F, // FSCAL0 Frequency Synthesizer Calibration

    0x09, // TEST0 Various Test Settings

    0x80, // RSSI Received Signal Strength Indication

    0x01, // MARCSTATE Main Radio Control State Machine State

    0x94, // VCO_VC_DAC Current Setting from PLL Calibration Module

    };

  • 0 in reply to Sverre
    Prodigy 100 points

    Hi, the above method works well  but with a disadvantage of range.How can i increase the range ?I did decrease the frequency deviation n it helps a lot in extending the range.I can't decrease the RX filter BW since  i need the full range to work. is range related to frequency offset and Intermediate frequency(IF).What other possibilities can i use in addition to that.Thanks.