Tool/software: TI-RTOS
Hi,
I am trying the determine the time required for a CC1310 to process an SPI_transfer(), particularly for a slave SPI configuration. I need to ensure that an SPI slave is always started before an SPI master starts another transfer. I cannot use hardware flow control due to lack of spare I/O, hence I'm currently using a "send and delay" control in the master. Is there any information on the worst case response times of the SPI slave task (i.e. the time that it takes to set-up the transfer before the chip select input goes low and the time to complete the transfer after the chip select input goes back high), particularly for a system where there are multiple tasks (at least two: the SPI task and a radio task). I appreciate that here may not be a definitive answer due to the OS task switching process.
I have a system set-up with two RF06 demo boards connected together via an SPI interface, with one as an SPI master and the other as an SPI slave. At both ends a simple task is configured that uses SPI blocking transfers within a loop. The master periodically issues an SPI transaction and waits for a period of time between transfers. Immediately prior to the SPI_transfer() a GPIO pin is set and immediately after the SPI_transfer() the GPIO pin is cleared - this can then be used to give an indication on an oscilloscope the SPI transfer timing for the master and slave ends. e.g. something like:
while(1)
{
PINCC26XX_setOutputValue(BoardLED1, 1);
transferOK = SPI_transfer(handleSPI, &transactionSPI);
PINCC26XX_setOutputValue(BoardLED1, 0);
CPUdelay(Slave_SPI_delay); /* for the master end only */
/* Some additional code */
....
}
I am measuring consistent SPI master set-up time (before the chip select goes low) of around 7us and a consistent SPI master completion time (after the chip select goes back high) of 16u to 26us (seems to be dependent on the data transfer length).
For the slave end, I can only independently measure the SPI slave completion time (after the chip select goes back high), which is inconsistent and varies from between 22us and 199us.
To ensure that the SPI link remains in sync, then I have to set a delay between transfers of at least 200us.
Are the above timings reasonable?
Is there a way of improving the timing?
Best regards,
Russell.