CC1101: CC1101 bit rate offset compensation?

The clock recovery loop (bit sync loop) contains a PI-regulator. The error input to this regulator is derived using a version of the Gardner algorithm and is updated once per symbol.

• The integrating path is used to adapt to a static offset in data rate (e.g. 103 kbps when 100 kbps is configured) and has a loop gain given by BS_KI and saturation limits given by BS_LIMIT. If BS_LIMIT=0 the integrating path has no effect on clock recovery.
• The proportional path is used to lock on the correct phase of the received symbols, i.e. to sample the symbols at the optimal time. Its loop gain is given by BS_KP. The proportional path cannot be deactivated and is necessary in order to allow clock recovery and frequency offset compensation.

The (scaled) proportional and integrating paths are combined and added to the configured data rate. In effect, it implements a kind of PLL that controls an internal data rate generator so that the generated symbol timing matches that of the incoming modulated sequence.

The saturation limit for the integral part of the feedback path which determines how great a data rate offset the clock recovery mechanism can compensate for. If the saturation limit is set too high, noise prior to signal reception can lead the data rate so astray so that many preambles are needed to correct it. In addition, the clock recovery loop can be configured to wait until the carrier sense condition holds true (FOC_BS_GATE_EN=1).