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CC3220S-LAUNCHXL: Wide Voltage Mode Application Circuit

Part Number: CC3220S-LAUNCHXL
Other Parts Discussed in Thread: CC3220S, CC3220R

Hi,

Could you help understand the following statement from Figure 6.1 from datasheet ?

PIN 45 and 46: For CC3220S and CC3220R parts, leave pin 46 un-connected (DNP L5 and R8). Pin 45 can be used as GPIO_31 if a supply is provided on pin47

PIN 47: For CC3220S, CC3220R device connect to VBAT and add 0.1uF cap

Does it mean to disconnect both L5 and R8 ? If R8 is disconnected than there will be no power on pin47. Also, the above note for PIN 47 requires to add 0.1uF, however on the Figure it is 10uF (C20). 

Could you re-phrase the above requirements?

Thanks,

David

  • Hi David,

    I am looping in one of our hardware engineers. Please expect a day for further response.

    Best regards,
    Sarah
  • Hi,

    It means for the CC3220S and the CC3220R the pin 46 is left as NC. 

    You have the option for these flavors to use pin 45 as a GPIO, to do this you need to power pin 47. if you don't need the extra GPIO you can leave pin 47 NC also.

    Regards,

    Charles O

  • Thanks. If pins 45, 46, 47 are NC, then the GPIO_PAD_CONFIG_31 contents is don't care and there is no need to drive pin 45, correct?

    One more question from the same figure, on the right side it shows the following pins as flash programming interface:
    CC_nReset, CC_GPIO_01, CC_GPIO_02, SOP0, SOP2

    What's the relation of CC_GPIO_01, CC_GPIO_02, SOP0, SOP2 to the FLASH_SPI _*pins?
  • Hi,

    Programming the serial flash is done via UART. the UART pins i believe are CC_GPIO_01, CC_GPIO_02. To boot into this programming mode you have to set the SOP (sense on power) pins to the righh configuration for the mode you are booting into.

    See section 5.10 of the datasheet.

    Regards,
    Charles O
  • Hi,

    Thanks. According to Section 5.10 all three SOP pins are used to configure the device operation mode. For flash load through the UART, the following 2 settings seem to set the device into flash load mode through the UART:
    SOP[2:0]=100
    SOP[2:0]=010

    Considering the above, could you help understand why SOP1 is missing from the flash programming interface group on Fig. 6-1?

    Also, could you confirm the following:
    If pins 45, 46, 47 are NC, then the GPIO_PAD_CONFIG_31 contents is don't care and there is no need to drive pin 45, correct? My concern here is that we don't miss anything that could cause unexpected leakage.

    Thanks,
    David
  • Hi,

    SOP1 needs to be included. The document will be updated.

    Please disregard previous comment about leaving pin 47 as NC, connect pin 47 to VBAT and add 0.1uF cap to ground, as shown in the datasheet.

    Regards,

    Charles O

  • Thanks. Another issue, capacitors 7 and 8 are marked 0.1uF on the schematic on Fig 6-1 but 100uF on the BOM on the next page (Table 6-1). Which one is correct?

    Are golden reference Gerber files available for the schematic on Fig 6-1? That would help a lot.

    Thanks,

    David