The expression for power dissipation in a processor is P f*V2. As system clock frequencies climb ever higher, nearing a state known as overclocking, efficiency is compromised and heat becomes a designer’s primary concern. Excess heat from the processor can lead to thermal shutdown, system power cycling, and/or permanent damage that can ultimately shorten the life of the processor.
Microprocessors, microcontrollers, DSPs, ASICs, FPGAs, and any other variation of digital load, do not require maximum power 100% of the time. In most applications, these digital loads, or “processors,” will be sitting idle the majority of the time. Even when idle, the processor may still be operating at maximum voltage and unnecessarily generating excess heat. One way to combat the negative impact of idle time is a technique commonly known as Dynamic Voltage Scaling (DVS).
When in an idle state, a processor’s frequency can be scaled back to save energy. Core voltage and frequency are directly correlated. The core voltage can also be decreased during idle states. This requires the ability to alter the processor core voltage in real time. DVS requires a feedback loop between the processor and the voltage regulator that is setting the core voltage. During idle states, the processor will send a signal to the regulator telling it to reduce its output voltage because lower-frequency operation within the processor is sufficient. The regulator output adjusts accordingly, lowering the processor core voltage and reducing its power consumption.
So how does the processor interface with the voltage regulator to scale the output voltage during both idle and over-clock states? There are multiple methods of implementation but one such interface protocol is VID, or Voltage Identification Digital. VID programmers can be used with virtually any point-of-load buck regulator or controller to vary the core voltage being supplied to the VID-enabled processor, for example the LM10010 and LM10011 by Texas Instruments.
Here’s how it works: The LM10010 receives a 6-bit code from the VID-enabled processor through a 4-pin VID interface (see Figure 1). This code features information that includes the core voltage value that the processor requires for its current state. The LM10010 then translates that code into an output current, on the order of µA, via its integrated DAC. This output current is then fed into the feedback node of the voltage regulator whose output is the core voltage of the processor. The additional positive current now flowing into the feedback node (highlighted in red in Figure 1) causes a reduction in the amount of current flowing through RFB1. This modification of the current through RFB1 adjusts the regulator’s output voltage to match the value in the 6-bit code supplied by the processor.
The LM10010’s 6 bits allow it to program the regulator output voltage to any of 64 different voltages within a range that is set with the feedback resistors used external to the regulator. The LM10011 adds the flexibility of implementing either four or six bits of resolution, both with a tighter output current accuracy compared to LM10010 (1.25% vs 3%). And the LM10011 is pin- and footprint-compatible with LM10010.
Figure 1: VID solution featuring LM10010, LM21215A-1, and a processor such as the TI C6000 DSP
An additional advantage of LM10010-11 is its cost-effective approach, as it can be used with a low-cost controller or regulator chosen at the discretion of the designer. If that immediately made you think of your favorite regulator or controller, that’s another great benefit - it can be used in tandem with the voltage regulator that you are already familiar with, assuming that voltage regulator features an externally divided feedback node (most do). The flexibility of being able to use LM10010-11 with virtually any regulator allows you to implement dynamic voltage scaling while also optimizing for cost and/or performance.
The TMS3206000™ DSPs with the SmartReflex™ interface from Texas Instruments is an example of a VID-enabled processor family with which a LM10010-11 VID solution can be implemented. However, a VID solution featuring LM10010-11 can be devised with any processor that has four spare lines of GPIO. The option to use LM10010-11 with virtually any regulator or processor presents a dimension of flexibility previously unknown in the world of VID. Customers can retain their existing design and add LM10010-11 to instantly and simply implement dynamic voltage scaling and reap the efficiency benefits associated with the technique.
Check out this reference design featuring the LM10010-11 with the TPS56221 25A integrated synchronous converter.
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