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PCM1865: PCM1865 master clock output

ManuelGómezGalánOpt
Prodigy 60 points
Part Number: PCM1865
Other Parts Discussed in Thread: PCM1807

Hello,

I am trying to substitute the ADC I was using in a design by the PCM1865. In my previous design I was using a 12.288MHz oscillator as clock source to the ADC, and then outputed this clock through the XO pin to a big DSP. This DSP is the "main" IC, so it uses this ADC as input for some signals. This DSP I am using generates the BCLK and LRCLK signals for its peropherics.

My question here is: can I use the XI pin for generating the MCLK signal and output it though the XO pin to my DSP, while using the inputed clocks BCLK and LRCLK?

Thanks in advance. Regards,

Manuel

  • +1
    TI__Mastermind 49260 points

    Hi Manuel,

    It might work depending on your layout, but I'm concerned about LRCLK and BCLK being synchronous with MCLK. You might be better off removing the Oscillator and using BCLK as an input to the PLL to generate the MCLK on the chip. This part can autoconfigure the PLL to whatever values it needs to be by detecting the BCLK and LRCLK frequencies.

    Best regards,

    Jeff

  • 0 in reply to Jeff McPherson
    Prodigy 60 points

    Hi Jeff,

    Many thanks for your fast answer. So, if I am understanding it correctly:

    • The suggested solution is to route the oscillator output to my DSP, mantain the same routing from the DSP to the ADC of the BCLK and LRCLK lines, and let the ADC auto-generate its clock when sensing those BCLK, LRCLK lines. Is this right?
    • If so, is there anything to be configured in the PCM1865 so it auto-configures its PLL parameters?
    • As seen in the Table 11 from page 42, on the 7th row it shows the desired configuration (48khz and 256 BCLK/LRCLK ratio). Can it be auto-configured, or should I change the settings in order to match the configuration from the 7th data row in the Table 13 from page 44 of the datasheet?
    • Also, for HW design, if I am not using the XI and XO pins, should they be left unconnected or pulled up/down?

    In order to give a little more of context, my DSP is in 8-channel TDM stream, where it sends 256 BCLK pulses per frame (i.e. for each LRCLK cycle). I am using it for a sampling frequency of 48KHz. The DSP can be configured also in 2-channel I2S, but I need the 4 ADC channels so I guess this mode would not fit my application.

    Also, I have more questions:

    • I am using this oscillator (ABRACON ASFL1-12.288MHz-LR) for the 12.288MHz MCLK. Would it be possible (and OK) to use this oscillator to drive the DSP chip, this ADC chip, and an auxiliary ADC (PCM1807)?
    • Is it possible to input a 2-channel signal (from a PCM1807) in format:
      • a) 24-Bit, MSB-First, I2S (FMT 0)
      • or b) 24-Bit, MSB-First, Left-Justified signal (FMT 1)
      in the DIN function (through GPIO1/2/3) and output with DOUT2 function (through another GPIO1/2/3 pin)? And, is it possible to do so while outputting through DOUT the 4 converted channels?

    Many thanks in advance! Best regards

    Manuel

  • 0 in reply to ManuelGómezGalánOpt
    TI__Mastermind 49260 points

    Hi Manuel,

    There's a lot of questions here so apologies in advance if I don't answer all of them at once.

    Your understanding is right. As long as CLKDET_EN (Page 0, 0x20) is set to 0 the PLL dividers will automatically configure. Table 11 is just showing which frequency ratios are supported. Table 12 gives more info into all the values that should be set. That is a reference for manual programming/crosschecking if something goes wrong with the autoconfigure. The PLL should sense the BCLK and LRCLK values and configure itself. 

    You can leave the XI XO pins floating since the muxes will disconnect those pins from the system entirely as the PLL is configured. Refer to the clocking tree to see this. 

    I can't advise on if the Oscillator will work with the DSP, but you should be able to drive the two TI devices with the same oscillator. A termination resistor may be necessary to prevent reflections.

    You can receive either format. The limitation is that it is a 24bit 2 channel signal.

    Each GPIO can be configured independently using registers 16 and 17. You can configure one to be a DIN and another to be DOUT2.

    Using the digital mixing feature found in 9.3.12.2.1 you should be able to send the ADC channels on DOUT and the DIN i2S signals on DOUT2. 

    Best regards,

    Jeff

  • 0 in reply to Jeff McPherson
    Prodigy 60 points

    Hi Jeff,

    Many thanks for your answer and sharing the knowledge. I see it clear now how to set the chip in case the MCLK fails to supply the three chips. Also, thanks for confirming that both formats for serial data in are supported.

    About the external ADC, is it possible to use this PCM1865 as slave (speaking of the clocks BCLK and LRCLK) and yet receive data? I guess it is ok as long as they have the same BCLK and LRCLK lines, right? (well, with the terminating resistors at the point where the lines are split for both chips)

    And last but not least, I cannot see clearly how to configure the Mixers (as you said from section 9.3.12.2.1 and Table 24 on page 69). How could I configure either:

    • DOUT for having (TDM format): CH1 for ADC1, CH2 for ADC2, CH3 for ADC3, CH4 for ADC4, CH5 for DIN_1 and CH6 for DIN_2?
    • or:
      • DOUT for having (TDM format): CH1 for CH1L, CH2 for CH1R, CH3 for CH2L and CH4 for CH2R
      • DOUT2 for having (TDM format): CH1 for I2SL, CH2 for I2SR

    Again, many thanks for yout time and dedication.

    Best regards,

    Manuel

  • 0 in reply to ManuelGómezGalánOpt
    TI__Mastermind 49260 points

    Hi Manuel,

    Yes Slave mode is fine as long as the data in and the ADC are synchronous. 

    The mixer is controlled with coefficient registers. This calculator tool will guide you on how to program it: http://www.ti.com/lit/zip/slac663

    Either format you propose should be possible, but I think the former is more straightforward. It appears like only one DOUT pin would be needed and you could mute the unused mixers with the digital PGA if they are not muted already by default. 

    Best regards,

    Jeff

  • 0 in reply to Jeff McPherson
    Prodigy 60 points

    Hi Jeff,

    Thanks for your answer. I cannot find the relation between the "Mixer" (which is configured with the file you sent to me) and the outputs. I think the mixer is to "sum" the signals, so they mix together (which is something I do not want).

    So, please let me know if I understad it correctly. For my purpose of converting from analogic to digital 4 differential signals, and output them in TDM mode in a 6-ch mode where the 2 additional serial-data-input signals are also transmitted, I should:

    • Power on the device
    • [Default] Set the device in slave mode (Page.0, register 0x20, bit 4 set to 0)
    • [Defalut] Set the device in auto clock detect mode (Page.0, register 0x20, bit 1 set to 1)
    • [Default] Set the receive mode to 24-bit (Page.0, register 0x0B, bits 7-6 set to 0b01)
    • [Default] Set the output data to 24-bit (Page.0, register 0x0B, bits 3-2 set to 0b01)
    • Set the input for ADC1_L to diff VIN1 (Page.0, register 0x06, bits 5-0 set to 0b010000)
    • Set the input for ADC1_R to diff VIN2 (Page.0, register 0x07, bits 5-0 set to 0b010000)
    • Set the input for ADC2_L to diff VIN4 (Page.0, register 0x08, bits 5-0 set to 0b100000)
    • Set the input for ADC2_R to diff VIN3 (Page.0, register 0x09, bits 5-0 set to 0b100000)
    • Set the output data to TDM mode (Page.0, register 0x0B, bits 1-0 set to 0b11)
    • Set the output TDM format to 6-ch (Page.0, register 0x0C, bits 1-0 set to 0b10)
    • (Check if any output TDM offset is needed when interfacing my DSP, with Page.0, register 0x0D)
    • (Check if any input TDM offset is needed when interfacing the external ADC, with Page.0, register 0x0E)
    • Set GPIO0 to MISO, GPIO1 to DIN (Page.0, register 0x10 set to 0x01100010)
    • Set GPIO2 and GPIO3 to GPIO for disabling their functionality (Page.0, register 0x11 set to 0b00000000)
    • [Default] Set the GPIOs to inputs (Page.0, register 0x13 set to 0b00000000)
    • Disable all the interrupts (Page.0, register 0x60, bits 3-0 set to 0b0000)
    • Disable the mic bias (Page.1, register 0x15, bit 0 set to 0)
    • Set the device in RUN mode (Page.0, register 0x72, bits 3-0 set to 0b1111)

    Still, it is not clear for me the output format as set in Page.0, register 0x0C, because it says:

    I do not know if those "sec_ADC_HPF" and "sec_ADC_LPF" are the external I2S data, it doesn't seems like it is. Also, with the Page.0, registers 0x06-0x09 configuration, I do not know if the order of the output chanels will be VIN1,  VIN2, VIN3, VIN 4 or VIN1, VIN2, VIN4, VIN3.

    Best regards,

    Manuel