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TPS2375: ESD Protection to Chassis Ground?

Wayne Eckertson
Prodigy 190 points
Part Number: TPS2375


I have a PoE PD design that fails to power up if the Chassis Ground and Return Ground are connected together at the bench power supply.  If the Chassis Ground and Return Ground are isolated at the bench power supply, the PoE PD device is successfully powered up.  I suspect that the PoE PSE is failing to negotiate with the PD due to leakage currents on the Chassis Ground.  I am measuring 0.58V across the Chassis Ground and Return Ground when the grounds are isolated.  When the grounds are connected, I am measuring 11nA of leakage current.  I suspect that the ESD clamps I have on my I/O pins (HDMI, RS232, and RS485) are the source of this leakage current.   These ESD protection devices are connected to Chassis Ground. 

I suspect the ESD protection devices but have yet to remove them all to prove my hypothesis.   The PSE device is customer owned and is a black box to me and I do not have access to the PSE schematic. 

Is there a recommended way (or way to avoid) of connecting ESD protection diodes in a PoE powered device?  Ap note SLVA233A appears to have recommendations for the PSE side but not the PD side.  Also it does not address I/O connectors other than Ethernet. 

Thanks for the help.

Wayne

  • 0
    TI__Prodigy 150 points

    Hello Wayne,

    I know you don't have the PSE schematic, but do you have one for the PD?

    If you are connecting Earth ground to return ground, then this can cause the device not to power up. I don't think the ESD clamps are the problem, as these were deliberately placed in the design (including on VSS return). The following user guide talks about different grounds and signals in the "Important PoE Signals" section. You might find this useful to you: PoE Powered Devices Debug Guidelines (ti.com) 

    You may also want to consider taking some scope shots of VDD to return and VSS to return. The voltage waveform between VSS and return should mimic the detection and classification phases of the PoE's operation. While these detection and classification phases are occurring, the waveform between VDD and return should be 0 V. Once the classification and detection phases are over (as per the VSS to return signal), the VDD to return signal should shoot up to whatever the intended value is (common for it to be 48 V, but really depends on PSE). 

    Let me know if I can be of further assistance.

    All my best,

    Atilla

  • 0 in reply to Atilla Sulker
    Prodigy 190 points

    I do have the schematic for the PD; it is now my design after inheriting it from a previous employee.  I am prepping the design for a spin.  I have attached a PDF with the appropriate PoE and connector pages. 

    Please review the schematic with the following changes and let me know if you have any other suggested changes.

     - The Chassis ground (GND_J1) and RTN ground are connected with R130 and R129.  I intend to replace these with 0.1uF caps.  From your comments, I believe this connection (these resistors) are the cause of the power up problem. 

     - Many of the ESD clamping diodes and connector shells are connected to the RTN ground.  I plan to isolate the connector shells from the RTN ground and connect the ESD protection device to these local chassis grounds.  TV1-TV8 will remain on the RTN ground plane. 

    - The mounting holes (MH1-MH5) will be isolated. 

     - I plan to move TV3, TV12, TV15, and TV14 to the connector side of the ferrite beads (FB11, FB12, FB10, and FB9) and connect them to chassis ground.  I will also move C158, C159, C231, and C229 from RTN ground to chassis ground.

     - I will connect the PG output of TPS2375 to the TEMP_SHDN# net.  I will also delete R53. 

     - Figure 10 of SLVA233A shows clamping diodes D2 and D4.  A note in chapter 4 of SLVAF74 also recommends ESD protection across VSS and RTN.  Would protection devices be recommended across VSS and RTN pins of the TPS2375?  Is there a recommended device or recommended TVS protection voltage?   

    Thank you for the help.

    TI_Forum_SCH.pdf

  • 0 in reply to Wayne Eckertson
    TI__Prodigy 150 points

    Hello Wayne,

    Thank you for the schematic. I will take a look at this and get back to you next week.

    All my best,

    Atilla

  • +1 in reply to Wayne Eckertson
    TI__Prodigy 150 points

    Hello Wayne,

    My apologies for the late reply.

    Based on the schematic, the resistors connecting return and chassis ground are zero ohms – this is, in essence, shorting the two grounds. In any case, it is not a good idea to connect the two grounds. You can try putting the capacitors in place of the resistors, and see what happens, but none of the designs we have connect chassis ground to return ground.

    Isolating the connector shells from the RTN ground and connecting the ESD protection device to the local chassis grounds is fine, as long as T11, T10, and T9 are kept.

    Moving TV3, TV12, TV15, and TV14 is fine, but I would leave C158, C159, C231, and C229 connected to return ground – otherwise, this would cause a short.

    Getting rid R53 and connecting the PG output to TEMP_SHDN is the right approach.

    Regarding a protection device between RTN and VSS: use the same thing as between VDD and VSS (i.e., TV9).

    Hope this helps.

    All my best,

    Atilla