Other Parts Discussed in Thread: TL16C550C, SYSCONFIG
(The HW used is actually 1352 LPSTK - but i found no such part number. But i hope it will be close enough)
We are confused about the UART HW FC signals together with low power on 1352:
Using the "XX" driver in "callback mode" we learned that we need to remove the RX callback for TI driver to allow sleep.
With the callback in place CPU runs and draws about 1mA+, without the consumption is reasonable.
So - removing the RX callback reduces CPU draw as mentioned above, the RXEN bit in the UART peripheral
is set to false, so the UART peripheral knows it is in a state where RX is disabled. But, the RTS flow control signal stays low in this mode (i.e stays asserted):
With HW FC the RTS should be de-asserted when UART RX is disabled - since other end of UART will send due to asserted RTS and data loss results.
Below i have attached a plot where "ARC GP1" (second plot from the bottom) is toggling from asserted to de-asserted (as expected) when we "flood" the UART FIFO.
However at min about 6:45 there is a 10s window where UART RXEN is set to false, but RTS is still asserted and this results in data loss.
Is there any workaround that we can use to make sure that RTS is de-asserted when the UART RXEN is set to false?

Best
Peter

