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TPS7A74: bias voltage

Fred Cheng
Expert 5970 points
Part Number: TPS7A74


Hi team,

1. does lower bias voltage leads to lower power consumption ?

2. my customer Vin is 1.8V, if we connect  Vin pin to bias pin which minimum is 1.7V,

is there a risk? what would happen if it  somehow drop to 1.7V

regards,

Fred

  • 0
    TI__Mastermind 37185 points

    Hi Fred,

    1. Yes, lower bias voltage leads to lower power consumption although this effect is very small if the LDO is powering a large load current.

    2. Yes there is a risk if you connect Vin and Vbias at these voltage levels, depending on your output current and output voltage.  The dropout of Vbias is 1.1V but can be as high as 1.3V.  but this is at max load (Iout = 1.5A).  Take a look at the dropout voltage levels below and determine if Vin = 1.7V - Vbias_dropout > Vout. 

    Thanks,

    Stephen

  • 0 in reply to Stephen Ziel
    TI__Expert 5970 points

    Hi Stephen,

    my Vout=0.75V, Iout=0.5A.

    you said the bottleneck is Vin - Vbias_dropout > Vout. 

    but even my Vin is 1.8V still fail this equation, 1.8-1.3<0.75.

    may I know what's the background of this equation?

  • 0 in reply to Fred Cheng
    TI__Mastermind 37185 points

    Hi Fred,

    The dropout for Vin is small and your input voltage will more than meet this:

    To design a low dropout (LDO) regulator, the internal error amplifier must have enough voltage on its rail to drive the pass device.  This voltage can come in the form of the output of an internal charge pump, or a BIAS rail input to the LDO.  The TPS7A74 uses the BIAS pin approach.  The pass device is shown as an NMOS transistor (see section 7.2) so it is the Vgs that is driving your dropout voltage.  Thus, Vout + Vgs (internal NMOS pass FET) < Vbias. 

    The Vin dropout of the LDO is dependent on the voltage drop across the pass FET.  This is just Rds(on) of the MOSFET multiplied by the load current Iout.  This is why the dropout of the input voltage is much smaller than the dropout of the bias voltage.

    Thanks,

    Stephen

  • 0 in reply to Stephen Ziel
    TI__Expert 5970 points

    Hi Stephen,

    can I see Vbias_dropout as the Vgs of internal NMOS?

    and it depends on the output current will be 1.1V to 1.3V.

    1.1V is its threshold voltage(Vth) I supposed?

  • +1 in reply to Fred Cheng
    TI__Mastermind 37185 points

    Hi Fred,

    Yes this is correct. Figures 6-33 through 6-36 that I provided previously is essentially the Vgs of the internal NMOS with respect to load current.

    Thanks,

    Stephen