UCC21737-Q1: Timing of active Miller clamp

This leads to a bad Gate Turn-On behavior: Gate voltage starts to increase while Miller-Clamp is still active. Then, Miller Clamp deactivates, causing ringing of the gate voltage. It seems like the driver has almost no deadtime between disabling CLMPE and enabling OUTH (red timespan in picture). Do you have any advice on how to optimize the timing? (Either faster Turn-Off of Miller Clamp, or delayed Turn-On of Gate.)

Hi Fabio,

Thanks for your interest on the UCC21737 device,

Can you please share the waveform?

Deadtime can be controlled by planning the INP and INN pins to be LOW, so its completely under the control of the application. The device internally don't have any additional deadtime. 

Thanks

Sasi

Maybe my question was inuaccurately written and Dead-Time might be the wrong word. The problem in my application is the almost not existing Time-Delay between disabling CLMPE and enabling OUTH. This Time-Delay is completely under the control of the Gate-Driver. (This has nothing to do with the Dead-Time between two different Gate Drivers tough.)

Hi Fabio,

I believe that you are talking about OUTPUT of a Gate driver toggled from LOW to HIGH with-out any delay even during external CLMP circuit.

The output will be following the INP. If the gate capacitance is high,  it will take time to completely discharge the Gate to VEE potential (during High to Low.) CLMPE will pull the gate to LOW only when the gate is ~2V. There are no defined spec between CLMPE activated and Gate to go high again. 

If the INP is toggled to high before Gate is fully discharged, then the OUTPUT will go High immediately after it goes low. There are no minimum time requirement between CLMPE go low and OUT goes high.

Is it possible to share your waveform, so that we can confirm some of the assumptions. Let us know if you have any additional questions.

Thanks

Sasi

Hi Sasikala, 

The Turn-Off of the Gate works fine, as the CLMPE releases the clamping MOSFET when the Gate voltage falls below a certain limit. This is a feedback- loop and the behavior is therfore controlled.

The Turn-On however behaves as follows in our circuit: 
CLMPE turns low, but almost imediately OUTH turns high. Our circuit recuires a few ns until the clamping MOSFET is open. When the clamping MOSFET opens, the Gate voltage is already charged to about 5V above VEE, so the clamping MOSFET already starts to conduct current (Weak shoot-through between OUT and clamping MOSFET). When the clamping MOSFET finally opens, it causes gate voltage ringing.

Hi Fabio,

As OUTH turns high is based on the INP going high timing, can the INP timing be adjusted per your system requirement to delay by few ns?

Is it possible to share your system waveform capture for us to understand the full picture?

Thanks

Sasi

Hi Sasikala,
Delaying INP would not help, as both  Turn-ON OUTH and Turn-OFF CLMPE would be eaffected. At the moment, we try to delay the Turn-ON OUTH without affecting switching speed, using additional gate-source capacitance and ferrite bead, but this solution is somewhat unsatisfactory. In my opinion, the Gate Driver from TI should add an additional delay in Turn-On OUTH of about 20ns. This would maximize the usability of the external miller clamp (CLMPE), especially with multiple paralleled MOSFETs.

Hi Fabio,

Thank you for your continued interest and sharing your criteria with us.

Gate driver OUT is controlled by INP (High or Low). I couldn't understand why INP H delayed couldn't be planned in this case. Whether its delayed by the system or the gate driver, both will impact the switching speed. So Its not very clear for me to understand why it couldn't be planned part of INP (on, off settings). Any waveforms will help us to understand the scenario better. Though UCC21737 doesn't have the capability, we are curious to understand your use case, so we can improve our future devices based on it.

As you indicated, increasing gate capacitance or increasing Gate resistance for the OUTH path all can be planned.

Let us know. Looking forward for your system waveform with and without INP H delayed to understand the differences.

Hi Sasikala,
Delaying INP would only delay the switching event as a whole. But in our test setup, the delay marked in red in the screenshot above seems to be too short. This delay is an inherent feature of the gate driver.

Hi Sasi,

Thanks for your reply. I was hoping that there are better means to solve the issue. Because of paralleled Power-Semiconductors, we have 3 clamping-Mosfets in parallel and we cannot reduce CLMPE capacitance any further.- So we will stick to your solution (2) and (3).

(For any future TI Gate Driver Designs, i would suggest to add  > 15ns delay between clamping release and gate turn-on.)

Thank you, appreciate it.

Fabio