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UCC28070: UCC28070

Part Number: UCC28070

Tool/software:

We have developed a 5 Kw PFC design based on the TI's data sheets, schematics (file name PMP4311A by Jack Zhang 50KHz clock) and TI's on line Webench Power Designer. However we find that there is no consistent design based on the required power output of the PFC

Webench link   webench.ti.com/.../32

The following resistor and capacitor values vary from data sheets to schematics and the Webench Power Designer. We are running the clock at 50KHz with a +/-10KHz dither rate.

  Part Designator from pin #                          5Kw schematic from Ti                                    Webench Power Designer.            Our Design

1  Dither                                                          15nF                                                                      150pF                                       330pF

2 RDM                                                             0 ohms                                                                   47K                                          47K

3 VAO                                                               100K series 1mfd // 0.1mfd                      113K series 1mfd // 0.15mfd                100K series 1.5mfd // 0.15mfd  

4 Vsens                                                            220pF                                                             3.3nF                                               3.3nF       Such variation

5 Vinac                                                             220pF                                                              1.2nF                                              1.5nF      Such variation

6 IMO                                                               30K // 1nF                                                        18K7                                               19K1

7 Rsynth                                                          300K                                                                 693K                                               68K        Such variation                      

8, 9 CSA, CSB                                                 1K 330pF to gnd                                               1K 220pF to gnd                             1K 330pF to gnd

                                                                         18R and 18R to gnd                                          33R2 and 33R2 to gnd                  18R and 18R to gnd     Such variation

10 Pk Limit                                                        6K8 to Ref 6K8 to gnd                                      3K65 to Ref 5K9 to gnd                 3K65 to Ref 5K9 to gnd 

11, 12 CAOA, CAOB                                        180pF to gnd                                                     330pF to gnd                                 220pF to gnd          Such variation

                                                                          15K series 2.2nF to gnd                                   4K75 series 2.2nF to gnd              4K75 series 6.8nF to gnd           Such variation

13 - 17 no issues

18 SS                                                                4.7mfd                                                             1.5mfd                                             10mfd // Our added schematic +++

19 RT                                                                160K                                                                150K                                                150K

20 Dmax                                                            140K                                                                140K                                                140K

We use 2+2 IGBT HGTG30N60A4D with 24R9 gate resistors driven from UCC27324s. Usual gate discharge 10K to emitters.

350uH inductors with STPSC40065C PFC diodes

60 amp input rectifiers with 3mfd bypass. Bulk capacitors are 3,300mfd and the PFC voltage is either 372v or 382v depending what half bridge supply is connected.

The Webench parameters I entered are 380v and 13A current

Now we come to the issues faced.

Pins 4 and 5 capacitor value has a wide spread value. Why? 

Pin 7 Rsynth varies from 300K to 693K and the only way we can get the 5Kw is to decrease this to 68K (39K gives 100% regulation whereas 68K PFC out drops from 382v to 365v).

The low value resistors on CSA, CSB are 18R in TI's 5Kw design and 33R2 in Webench. We have to use 18Rs to get the power. At 33R the PFC voltage drops to 250v!!!!!

Pins 11 and 12 such variation of part values.....why?

Now to the big one. 

When I first developed the UCC28070 design I placed a 1mfd SS capacitor. The turn on current was huge even with a 2 second relay bypass of the 110R in series with the AC input.

I had to add in a real soft start circuit which allows three things to occur.

First the in rush current to pre charge the bulk capacitors to the peak of the mains voltage is very low due to the 110R resistor.

Second, my soft start circuit (see below) allows the bulk caps to charge up very slowly to their full PFC value

Third the 6Kw half bridge supply which has 50,000mfd on it's split rail supply also charges slowly due to the UCC28070's dead time being so high for the first 30 seconds after power up.

Thus there is no turn on surge from the mains at all.

This SS circuit is an NPN transistor held on with a base resistor to +15v. Emitter to common. It's collector is connected to the SS pin 18 via a 47mfd in series with a 5K9 resistor.

A 30 second timer will shut off the base of the NPN and allow the full duty cycle to be effective.

Efficiency at 4Kw load is 97% and drops to 88% at about 500watts of load.

The resistor value at Rsynth is critical to output power and below 68K the current increases with the same resistive load on the PFC output.

The CSA, CSB low value 18R resistors are critical for good power delivery yet data sheets and Webench show 33Rs for this.

The big question is: Why can TI not supply a tool where the designer chooses the few parameters required for their particular design and the toll should spit out the balance of the passive parts.

Webench fails to do this.

Regards

Stephen Mantz

Zed Audio Corp.

email:  smm@zedaudiocorp.com

  • Hello Stephen, 

    I'll try to answer your major concerns, but I will not individually address every difference that you have pointed out.  Instead, I'll make a generalized statement that, unless everyone uses exactly the same design criteria for selecting each and every component, no two designs will ever be identical because different designers use different design criteria or have more or less experience with the topology, the controller, the power train components, or all of the above.   The author(s) of the datasheet, the Webench program, and the PMP4311A reference design are all different people and simply didn't use the same criteria for everything.  On occasion, someone can just make a mistake, but the consequence may be minor enough that the mistake may go unnoticed. 

    In my opinion, I recommend to follow the UCC28070A datasheet design procedure since it has the most recent updates (as of Dec 2023).  The UCC28070 and 070-Q1 datasheets, the Excel tool, and Webench, and some other design-aid files have not yet been brought up to date, mainly due to limited resources. 

    I do agree that Webench could be improved, but I disagree with the notion that a designer has only a few parameters to decide and Webench should spit out the rest of the design.
    It is my opinion that the power supply designer should decide all of the parameters and design margins to be applied and the tool should just "do the math" to provide the component recommendations.  If you simply provide Vin, Vout, Pout, and fSW, you will get a design as the Webench authors envision the design criteria to be, not necessarily what you want or expected it to be. 

    Regards,
    Ulrich

  • Dear Ulrich,

    Thanks for your reply.

    The two real issues I have are with Resistor Rsynth which is always seems to be shown at values well above 100K. With this type of value the PFC will not allow me to deliver 4Kw at 380v. It seems that Rsynth, for me at any rate needs to be 47K-68K for good power delivery.

    The formula on page 18 of SLUS794A gives me a value of 304.5K for Rsynth.

    My current xfrs are 1:200, Inductors ate 350uH, Kr = 0.00783 and Rs are 18R.

    In addition the "loading resistors" on CSA/CSB cannot be any higher than about 22R, also for good power delivery.

    I checked through the various PDF files regarding the UCC28070 and checked my R and C values and even though there are differences on some of them, the efficiency does not vary much. The only item affected is power by the above resistors.

    BR

    Stephen

  • Hello Stephen, 

    In general, the value of Rsynth should be adjusted up or down around the calculated value for purposes of optimizing THDi, and should have only a secondary or mild effect on power delivery.  The purpose of Rsynth is to program the synthesized down-slope of the inductor current (red dashed lines in Figure 19) to mimic the actual inductor current during this switching interval.  The combined measured currents at the CSx inputs plus the synthesized down slopes recreate the inductor current signal input to the current amplifiers (CA) which produce an error output of how much the averaged inductor current differs from the IMO reference signal. 

    If Rsynth is too high, the down-slope is shallow and the synthesized signal is overstated compared to Vimo, so the current loop scales back PWM and the voltage loop has to increase VAO to compensate for the reduced PWM.  If VAO hits the internal 5V clamp, no more increase in output power is possible for a given input voltage and Vout falls. 
    Conversely, if Rsynth is too low, the down-slope is deep and the synthesized signal is understated compared to Vimo, so the current loop would widen PWM and the voltage loop would have to decrease VAO to avoid pushing out too much power and causing an OV condition.
    Note that at high input voltages, the PWM duty cycles are relatively narrow over most of the line cycle, so adjusting the down-slope will have a big affect over each switching cycle since the down-slope then constitutes most of the current signal.  

    The true controllers of throughput power are Rimo and Rs (along with Nct), but actually Rimo is calculated based on previously selected Rs and Nct values, along with Iimo.  And I think that Iimo is calculated  properly for "universal line" cases which includes low-line input, but is NOT calculated properly for high-line only cases.   For a 5kW application, I'm guessing that your AC input is high-line only.  

    If Iimo is incorrect, then Rimo will also be incorrect, and power delivery will be affected.  Since you have to reduce Rsynth to get sufficient power out, it suggests that Vimo is too low, which means Rimo is too low because calculated Iimo is too low. 
    Looking at Equation (13) (page 21),  Vvao = 5 at full output power (including rated power plus any additional power for margin and rapid transient response), Vvinac = the peak of your lowest input voltage scaled by Kr, and kVFF = the value of the level within which the Vvinac peak falls.  Typically this may be level 6 (kVFF = 2.199) but may be higher or lower depending on your particular lowest line. 
    And something that is not as clear as it should be: 
    The UCC28070 always powers up with kVFF default to 3.857 (level 8) and drops down to the appropriate level after a zero-crossing has established the true input peak.  The Level thresholds in Table 1 are based on rising input voltage.  Levels increase when input voltage peaks cross the listed thresholds. When input voltage falls, the falling thresholds are 5% lower than what is shown in Table 1.  So at power up, the level at which the lowest VINAC peak falls to depends on crossing the falling thresholds.   Getting the right Iimo depends on these factors.    

    The CSx loading resistor values (Rs) should not be chosen for power delivery, but for signal level.  This is (admittedly obscurely) discussed in the middle paragraph on page 33.  Setting the max average current voltage across Rs to ~3V provides high SNR yet should leave plenty of room for the ripple component of the inductor current to stay within the linear range of the CA inputs.   Rimo is then calculated (with appropriate Iimo) to match this voltage. 

    Rs and Cs added for filtering should be sized to filter out only switching noise, but not degrade the signals.  They shouldn't affect power throughput. 
    Rs and Cs for I-loop and V-loop compensation affect loop stability, but shouldn't affect power throughput. 

    By the way, the SLUS794 datasheet is currently at rev F, so your rev A datasheet is rather dated.  Pick up the latest copy here: https://www.ti.com/lit/gpn/ucc28070 

    But please actually use UCC28070A for the update design procedure to accommodate high-line only applications:
    https://www.ti.com/lit/gpn/UCC28070A 

    Regards,
    Ulrich

  • Dear Ulrich,

    Let me take a look at this this evening. I shall go through this updated data sheet and check my values.

    The power supply is rated to work from 100v -265v AC so I guess SLUS794F will be appropriate.

    BR

    Stephen

  • Dear Ulrich,

    I down loaded and compared the new PDF for the UCC28070. As far as the various formulas are concerned, I see no difference. I re calculated all my passive parts. I kept the two RS at 18R each. For Rsynth I put in a 500K series 39K. I also changed the dither capacitor to 680pF and resistor to 91K to have a 10KHz dither with the 50KHz clock.

    I am running off 208v AC mains as the 120v cannot support the highest load.

    Loaded the PFC which I trimmed to 272volts due to my requirements in the half bridge switcher that my audio amplifiers will run from a +/-185v rail.

    As a note I also set the PFC to 384 volts but the loading of the PFC made no difference.

    Loaded the 272v PFC output at 516 watts and the 272v remained constant whilst varying Rsynth between 39K and 340K.

    Loaded the 272v PFC output at 823 watts and the 272v remained constant whilst varying Rsynth between 39K and 340K.

    Loaded the 272v PFC output at 1383 watts and the 272v did NOT remain constant whilst varying Rsynth between 39K and 340K.

    Loaded the 272v PFC output at 3,953 watts and the 272v did NOT remain constant whilst varying Rsynth between 39K and 340K.

    In the 3,953 watt test I had to reduce Rsynth to 70K to allow the PFC output to remain within 4 volts of the 272v output.

    You wrote: For a 5kW application, I'm guessing that your AC input is high-line only. You are correct as a 120v outlet cannot support this.

    The formula for calculating Rimo shown on page 22 is:  0.5 * 25 * 18/200 * ~ 200uA = 5K6  am I totally off here?

    Some of the PDFs I have downloaded which are TI designs show Rimo between 24K and 30K

    I am really confused about this

    Can increasing Rimo from my 19K ohm to 30K make this large difference in power delivery?

    BR

    Stephen

  • Hello Stephen, 

    I too am a bit confused because you are introducing new information and configurations that were previously not presented. 

    You did mention in your last reply that your minimum input voltage is 100Vac.  (Is it truly 100Vrms, the nominal low voltage of Japan, or is it 90~85Vrms -10 to -15% of nominal 100Vac?  Or -16.7% of 120Vac?  Because 265Vac is basically +10% of 240Vrms, a standard US voltage. It is confusing to have mixed tolerances.)  But not mentioned was that Pout will be reduced at low line.  The stock design equations do not account for changes in output power and/or output voltage with line voltage. 

    That can be done, but it is best to have all of the design target details up front.  You may have to actively change a few parameter values (Rimo, Rs, Rsynth, etc.) depending on what Vin and loading situation the PFC is in.  The optimized values would be calculated separately. 

    For this question: "... calculating Rimo shown on page 22 is:  0.5 * 25 * 18/(200 * ~ 200uA) = 5K6  am I totally off here? " the equation result is correct (parentheses added) with the values shown, but Rs = 18||18 = 9R (from earlier post) so Rimo would be even lower.  But it is based on Iimo = 200uA and Ini(pk) = 25A, and I wonder how those numbers were calculated.  They may not be the correct values for the line and load conditions that you are working with.   

    For this: "Can increasing Rimo from my 19K ohm to 30K make this large difference in power delivery?", Yes, to a point.... The voltage on the IMO pin determines the target reference voltage for the current-error amplifiers (CA) to modulate the PWM to get the CSA and CSB voltages to match it. 
    For a given IMO current, if you almost double Rimo, then you almost double Vimo, so you almost double the inductor currents, hence a large differnece in power delivery. The limitation is that Vimo higher than ~3.7V will not have any effect because the CA inputs saturate around there, so changes in Vimo > 3.7V will no longer change the CA outputs. 

    To move forward, please provide your complete set of input and output requirements.  For two input voltage ranges, two output power ranges, and two output voltages, there may not be a single set of values that works for all variations. 

    Regards,
    Ulrich 

  • Dear Ulrich,

    My apology for not being clear enough.

    A quick correction. The resistors "RS" are each 18 ohms not 9 ohms.

    I understand that the power supply is limited by the available power from a wall socket.

    Japan at 100v you can draw a max of 20 amps = 2Kw

    USA at 120v you can draw a max of 20 amps = 2.4Kw

    220-250v seem to be typically 13A to 20A for 2.8Kw to 4.4Kw

    Because this product is sold world wide and the most common places sold to are 220v-240v.

    120v and 100v are our second tier of clients.

    I fully understand that Pout is limited by the wall socket.

    The 85-265v is really not applicable as I wrote above.

    I do my testing at 120v and 208v (The 3 phase in our factory is 208v and what I do is use two of these phases to give me 208v with 20A breakers.

    My first requirement is 100-120v 2Kw to 2.4Kw

    My second is 220-240v 2.8Kw to 4.4Kw

    My PFC voltage let us use a median of 378v. The reason is that one product I have PFC Vout at 380v +/-1% and the second I lower it to 372v +/-1% to accommodate my half bridge transformer winding ratio.

    Hope you can help with calculating Rimo and Rsynth together with Rs (2 places)

    At the moment I have Rimo at 19K, Rsynth at 68K and Rs each 18 ohm.

    Regards

    Stephen.

  • Ulrich, 

    I forgot to ask.

    Can ripple steering be applied to this two phase PFC?

  • Hello Stephen, 

    Thank you, you have clarified your goals quite a bit for me. 

    First, I must apologize about Rs = 9ohms: that is my mistake; I was confusing two 18R resistors in parallel for a single Rs, probably because of another design that I am concurrently supporting. 

    Second, I now understand the 380V output vs 372V output scenario. ( Note, several times you listed it as 272V which didn't make sense with a 240Vac input.)

    Third, I now understand how your output power will be limited by the maximum current available from the line socket.  
    I feel that I must caution you (or at least, others that may be following this thread) that the 20A line rating is derived from the 20A circuit-breaker protecting the branch circuit and that the National Electrical Code and UL expect that the branch loading will be limited to 80% of the outlet and braker ratings.  This is to allow headroom for the load current to go up when there is a sag in the voltage.  I'm not telling you what to do; I mention this to expose the risk of running a load at the maximum rating of the branch circuit while at nominal line voltage.   
    On the other hand, your application is an audio amplifier, and hopefully the load may have brief high-power peaks but will not be a continuous steady-state 4.4kW of sound power!

    That said, I disagree that "The 85-265v is really not applicable..." as you state above.  The 265V number historically comes from a 264Vac max rating which is from 240Vac +10% in the US (and elsewhere).  The 85Vac number comes from having additional margin to 100Vac -10% in Japan.  (Basically, OEMs specified 90Vac ~ 264Vac from their subcontractors and the subcons designed for 85~265 to guarantee that they'll meet the 90~264V requirements.)
    The point is not a history lesson, but that if you advertise 2kW output at 100Vac in Japan, they will expect the same 2kW if their line sags -10%, but to do that the line current must go up +10% to 22A and that may trip their 20A circuit breaker if the 2kW is sustained longer than the circuit breaker can withstand.   

    Normally, a maximum load power is specified and the lowest input voltage is where the PFC must be designed.   
    In your case the maximum input current is the defining factor, not Pout.  The maximum current doesn't change with sagging voltage, so for low-line Japan, 20A x 90Vac = 1800W max ( or, x 85Vac = 1700W max).  We have to settle on the minimum input voltage to design to, which dictates the power level for that voltage and leads to most of the control parameters. 
    Note: High-line Japan is nominally 200Vac +/- 10%, or +/-15%, or +10,-15%, so high-line only designs are often spec'd at 180Vac or 170Vac minimum input. 

    Normally (again), a PFC is designed for a maximum power which is held from the lowest line to the highest line; so a single set of component values.
    In your case you want to double the power when you double the voltage.  These are really two different designs, with 85V as low line in one case and 170V as low-line in the other.  But a complicating factor is that you want max power to increase as the voltage increases and that is something that I have not done before.  I don't know if it can be done... simply. and cheaply.  I'm certain that it CAN be done with sufficient complication, time, and money (because the concept does not violate any laws of physics).   I'd like to think about how, but I don't have a lot of time available to ponder it. 

    But I did ponder it for a few more minutes, and I think it might be simple enough: if VINAC is held constant; set at the low point of the low or high AC input range of the locality where the equipment is (that is, set for 85Vac in low-line countries and set for 170Vac for high line countries) then the kVFF factor will not change to reduce the input current as the line goes up in that range.  VAO will be strictly a function of output power, with no vestige of line variation within a kVFF level.  VAO = 5V can be set at the max power (= max input current) at the lowest line voltage, and as line-V goes up, VAO = 5V still equals the max input current set at the low line (of the range).  You will need something to detect which line range the gear is in and change the fixed VINAC voltage appropriately to match...  actually no you don't!  A single fixed VINAC value should work world-wide, since the IMO equation will drive the maximum inductor current at VAO = 5V regardless of what the AC input voltage is (since VINAC variations have been taken out of the picture).   

    This is pleasantly surprising to me. This is really just taking the line-voltage feedforward out of the current loop. But it also takes VFF out of the voltage loop, so loop gain will no longer be (semi-)constant, but will vary with the square of Vin. Double Vin = 4x the gain.  85Vac to 265Vac is about 1:3, so gain will vary by 9x worldwide.  You'll have to be careful about loop compensation. 
    (Ultimately, this took me another half-hour to think through, and I'm not sure that I've been thorough. There may be unthought-of side-effects. )

    As for ripple steering, I am not competent to comment much on this topic.  I remember there was some flurry of interest in the 80's or 90's, then it seemed to go away.  I never worked with it, but I imagine that if it could be made to work with a simple DC-DC boost topology, then it can probably also work in a boost-PFC topology, with any number of phases.  But I don't know how it would be done.   

    Regards,
    Ulrich

  • Dear Ulrich,

    I understand the power available from the different wall sockets from 100 to 250 AC. The power supply is limited by these wall sockets ability to deliver the power and also by the class A/B amplifier hanging on the power supply. Typically the efficiency of the amplifier is about 70% at maximum continuous sinewave power which in the case of the mono amplifier is about 1,780 watts. So it requires that the power supply deliver 2,542 watts at this level. 

    The rub is that when test reviewers run their silly sine wave tests they want to see how much power the amplifier can deliver. This power will be solely determined by the country's wall socket to deliver the power and not the PFC's ability to deliver the power.

    So in Japan as an example, the amplifier is not capable of delivering it's rated paper spec power of 1,500 watts never mind it's power at clipping (1% THD) simply due to the limitations of the electrical supply.

    The fact is that the PFC works from 90-260v AC is simply a by product of the PFC and its design.

    I test the PFC from 90v to 240v AC with the use of a large variac which I run from my 208v. This 208v AC is actually derived from two of my three phases in the factory. So there is no neutral wire involved. I made up a power block which simply takes the "hot" from two of the phases.

    The bottom line is that I am still confused that I have to choose Rsynth to be 68K, RS each 18R to get out the power from the PFC.

    Would you like me to send you my schematic?

    Please advise how attach a PDF file to this forum?

    Regards

    Stephen

    PS. I have tried ripple steering on a class D amplifier and it does wonders BUT the class D must be driven by a clock, whereas my designs are self oscillating and ripple steering does not work.

    I also tested it with an old IRS1150 chip and it did reduce the ripple on the bulk caps.

  • Hello Stephen, 

    Let me get a few quick things out of the way:
    1.  I do understand about running the PFC input from 2 hot phases of a 3-phase line, no neutral involved.
    2.  If ripple steering works with the IR1150, it will work with the UCC28070, although the interleaving may or may not complicate things a little. 
    3.  It would be helpful to view a PDF of your PFC design.  To attach it, click on the "Insert" drop-down menu at the bottom of the Reply dialog box, then select "Image/video/file".  A new dialog box opens; click on the "Upload" button just under the empty File/URL box near the top.  That will open up a Windows window where you can navigate to the file and "Open" it.  That really just loads the file into the the E2E Reply box where the cursor is.  Click "Ok" to finish. 

    Rsynth should not be instrumental in setting the output power available from the PFC.  If it is, something else is amiss.  Rsynth influences the current synthesizer output waveshape which directly affects the THDi.  But it could have an oblique influence on the power if some other parameter was stuck at a limit.  (One such limit is when VAO rises to 5V, it is internally clamped there and can't rise higher.) 

    First, let's establish what is the maximum output power that you want from the PFC when the input is 90Vrms?  This maximum power number should already include any margin (like 110% or 120%) to the nominal Pout rating.   
    That Pout(max) is divided by low-line efficiency (93% ??) to get the Pin(max).  Assume PF = 1, Pin(max)/90Vrms = Iin(max)(rms).  Each inductor sees Iin(max)(rms)/2 and the peak average inductor current = 1.414*Iin(max)(rms)/2.   Inductor ripple current is not involved yet.  

    Your CTs are 1:200, so peak average current into each Rs is (1.414*Iin(max)(rms)/2) / 200.  Rs value is chosen so that the CSx voltage at this current= 3V.  
    So Rs = 3V / ((1.414*Iin(max)(rms)/2) / 200).  That settles Rs. 

    Rimo is determined by choosing Rimo so that you get the same 3V when Iimo = 17uA *(kr*1.414*90Vrms) * (5V - 1) / kVFF corresponding to (kr*1.414*90Vrms), where kr is the VINAC divider ratio.
    (Normally kr is the same as the VSENSE divider ratio, but it can be different if you know and accept the consequences of making them different).   
    When Rimo is selected this way, you will get the power out that you designed for provided that Iin(max) is available. 

    If input-kr for VINAC (call it kri) is different from output-kr for VSENSE (call it kro) then the Rsynth equation is not correct, since it does not account for differing kr's.  If kri is not much different from kro, then the Rsynth equation can be a good starting point, and THDi can be optimized empirically by adjusting the Rsynth value up or down as needed.  If kri is greatly different from kro then I'm not sure how to set Rsynth.  I'll have to think about it. 

    Regards,
    Ulrich  

  • Dear Ulrich,

    Sorry for my late reply but I had to fly to Texas for a meeting.

    I shall send you my schematics this evening

  • Thank you, Stephen, 

    I'll need a while to peruse those files.  Maybe I can make a response later today.

    Regards,
    Ulrich

  • Dear Ulrich,

    I have not received a reply regarding my schematics.

    Regards

    Stephen

  • Hello Stephen, 

    I'm sorry, I dropped the ball on this one.   I didn't get the time I thought I would get, then lost track of this issue.

    First though, I realized that my idea of fixing the VINAC to a constant voltage was a dumb idea.  We need the VINAC sine shape to generate the sine reference signal at IMO.  I was thinking about a fixed RMS value, but forgot about the sine shape aspect of it. 

    Secondly, I still don't have the time I need to go through your schematics thoroughly.  I will be in office only in the morning tomorrow, then out until next Monday.  I'll try to have a useful reply for your early next week. 

    Regards,
    Ulrich