BQ76972: Measuring strange stack voltages in stacked design

Hello Vadim,

Is there a reason for not connecting the current sensing resistor and FETs yet? I think this previous post may be helpful: Stacked Design Bring-up Wrong Cell Measurement.

Best Regards,
Alexis

Hi Alexis, 
Thank you for the tip...  We did solved Missing Current+ to GND shunt issue previously too as we've experienced negative voltage measurements on the top BQ.

The FETs and Current sensing resistance are not connected because our design is split in 2 boards:
Processing board (2 BQs MCU + connectivity stuff)  and Power Board with MOSFETs  thermistors and current sensing resistor.  
The power board was not ready 3 days ago.
What we do not understand is why the Sum of 2 stack voltages (as measured by BQs) is not equal to the supply voltage. 
And the delta grows as we grow suplly voltage

Hi Alexis,

We did test today with the power board. The FET control is working and the cell voltages have the correct values.

The stack voltage remain incoherent with the sum of cell voltages (It starts to be wrong at ~28V).

Could it be a gain to set or a missing calibration?

How can a stack voltage be greater than the input bat?

Can the reference/ground be incorrect in our configuration or schematic?

Thanks,
Ronan

As a reminder our design is based on TIDA-010247 https://www.ti.com/tool/TIDA-010247#overview which seems to be optimized for 48V batteries.

Ronan

Hello TI Team,

We did perform a calibration of voltages today.

The stack voltage is now coherent but the gain value is around  ~17000 which is very different compared to the factory values (~34000) for both BQs.

Also the pack voltage of the bottom BQ is coherent when the FETs are closed but is non zero when FETs are opened.

Do you have any advice or comments?

Thanks,
Ronan

Hello Alexis_H,

It looks that with the TIDA-010247 the calibration of Pack and LD Bottom BQ voltages should be done differently.

There is a voltage divider for the pack voltage on the BQ bottom:

Ratio ~0.5 (600k / 1200k)

There is voltage divider for the ld voltage on the BQ bottom:

Ratio ~0.76 (2000k / 2600k)





What is the purpose of those dividers for the bottom BQ?

We are trying to integrate those voltage dividers for the calibration of the bottom BQ pack and ld voltages.

By any chance, do you have a code sample of the calibration for this TIDA?

We were not able to find the implementation of `void BQ769x2_Voltage_Calibration();` function declared here: https://github.com/TexasInstruments/mspm0-sdk/blob/main/examples/nortos/LP_MSPM0G3519/demos/bq769x2_TIDA010247/BQ769x2_Configs/BQ769x2_protocol.h#L546

(Related to this post).

Thanks,
Ronan


CC Vadim Lebedev
CC Luis H. S.

Hello Ronan,

Ronan Chauvin said:

Also the pack voltage of the bottom BQ is coherent when the FETs are closed but is non zero when FETs are opened.

The device includes its own factory gain trim; however, it can be optimized when customers calibrate the device to their system/design.

Ronan Chauvin said:

The stack voltage is now coherent but the gain value is around  ~17000 which is very different compared to the factory values (~34000) for both BQs.

Is this with a load/charger attached or is this with no load and PACK+/PACK- pins are floating?

Ronan Chauvin said:

What is the purpose of those dividers for the bottom BQ?

The PACK and LD pins have a max rating of VSS+85. As mentioned in the image, you would want to change the resistor out to adapt to different PACK voltages as this reference design is for up to 32S and up to 1500V ESS applications. Some users may use less that 32S or lower voltages, so the PACK pin resistors do not need to be as high.

Ronan Chauvin said:

By any chance, do you have a code sample of the calibration for this TIDA?

We do not have any sample code of the calibration for this TIDA.

Best Regards,
Alexis

Alexis_H said:

Is this with a load/charger attached or is this with no load and PACK+/PACK- pins are floating?

It is without a load or charger so PACK+/- pins are floating.

A very different gain value compared to factory trim looks normal for Pack/LD voltages (due to voltage dividers) but seems strange for Stack voltage, no?

Alexis_H said:

The PACK and LD pins have a max rating of VSS+85. As mentioned in the image, you would want to change the resistor out to adapt to different PACK voltages as this reference design is for up to 32S and up to 1500V ESS applications. Some users may use less that 32S or lower voltages, so the PACK pin resistors do not need to be as high.

OK our design is 24V -> 72V so no divider will be required.

Thanks,
Ronan

Here is an example of a calibration output for BOTTOM and TOP BQ.

Calibration Results Comparison BOTTOM
----------------------------------------------------------------------
Parameter                 Old Value            New Value           
----------------------------------------------------------------------
Cell 1 Gain                 12120                12290               
Cell 2 Gain                 12120                12075               
Cell 3 Gain                 12120                12058               
Cell 4 Gain                 12120                12040               
Cell 5 Gain                 12121                12056               
Cell 6 Gain                 12121                12053               
Cell 7 Gain                 12121                12021               
Cell 8 Gain                 12121                12006               
Cell 9 Gain                 12128                12059               
Cell 10 Gain                 12128                1                   
Cell 11 Gain                 12128                1                   
Cell 12 Gain                 12128                1                   
Cell 13 Gain                 12128                1                   
Cell 14 Gain                 12128                1                   
Cell 15 Gain                 12128                1                   
Cell 16 Gain                 12128                12037               
Cell Offset                0                    -16                 
VDiv Offset                0                    -640                
TOS Gain                   33486                17131               
Pack Gain                  33481                15918               
LD Gain                    34834                14807
----------------------------------------------------------------------

Calibration Results Comparison TOP
----------------------------------------------------------------------
Parameter                 Old Value            New Value           
----------------------------------------------------------------------
Cell 1 Gain                 12121                12265               
Cell 2 Gain                 12121                12226               
Cell 3 Gain                 12121                12243               
Cell 4 Gain                 12121                12254               
Cell 5 Gain                 12121                12242               
Cell 6 Gain                 12121                12205               
Cell 7 Gain                 12121                12241               
Cell 8 Gain                 12121                12253               
Cell 9 Gain                 12125                12238               
Cell 10 Gain                 12125                1                   
Cell 11 Gain                 12125                1                   
Cell 12 Gain                 12125                1                   
Cell 13 Gain                 12125                1                   
Cell 14 Gain                 12125                1                   
Cell 15 Gain                 12125                1                   
Cell 16 Gain                 12125                12223               
Cell Offset                0                    22                  
VDiv Offset                0                    -663                
TOS Gain                   34238                17211               
Pack Gain                  34387                17235               
LD Gain                    32611                9544
----------------------------------------------------------------------

Hello,

Our engineers are out of office and will get back to you next week.

Best Regards,

Luis Hernandez Salomon

Hello Luis,

OK thanks for the info.

The calibration results above is done with the following "target" voltages (FETs closed):

1/ Power supply 30V:

BOT STACK = 15V PACK = 15V (voltage divider ~0.5) LD = 22.98V (voltage divider ~0.76)

TOP STACK = 15V PACK = 15V (TOP BAT IN) LD = 13.99V (divider + diode ratio 0.97)

2/ Power supply 48V:

BOT STACK = 24V PACK = 24V (voltage divider ~0.5) LD = 36.7V (voltage divider ~0.76)

TOP STACK = 24 PACK = 24V (TOP BAT IN) LD = 22.25V (divider + diode ration 0.97)

We also tried a calibration that doesn't integrate the ratio for the bottom BQ (i.e PACK/LD directly at a target voltage of 30/48V):

TOS Gain                   33486                17162               
Pack Gain                  33481                32285               
LD Gain                    34834                19500

Which then gives the values:

PS 30V: Pack 24V, LD 19.6V (Stack 15V OK)
PS 48V: Pack 42V, LD 37.8V (Stack 24V OK)

Talk to you next week,
Ronan

Hello Luis H. S. / Alexis_H,

Any news from your engineers?

Ronan

Hello TI Team,

It looks we would need specific "VDiv Offsets" for Stack/Pack/LD to entirely compensate via the calibration.

Do you think it is something we should consider (Could be done by the host MCU)?

Thanks,
Ronan

Hi Luis,

I am sorry for pushing, but is there any chance that the engineers will have a look this week ?

Regards,

Hi Alexis_H,

We are still stuck with this issue, do you think we can get support on this matter ?

Regards,

Luis H. S., Alexis_H Kind reminder!

Hello Alexis_H,

Thanks for the links. We are using the exact same Python script as provided in the calibration guide.

It looks the « stacked design » of two BQs requires a specific calibration procedure for Stack/Pack/LD from my understanding. But the reason doesn’t look clear.

The calibration with a « mono design » on the evaluation board doesn’t generate such important gains/offsets and the Stack/Pack/LD voltages are quite correct without any calibration.

Thanks,

Ronan

Hello Ronan,

The Python script provided in the calibration guide was made with a mono design in mind when doing so, however, the idea behind it should be similar. Is the calibration for the stacked design helping with what you are seeing now?

Best Regards,
Alexis

On the stacked design, it does help for the stack voltage.

For pack and ld voltages, it doesn’t compensate all the error.

Ronan

Hello Ronan,

Just to double-check, is this still with the current sense resistor and FETs not connected?

Best Regards,
Alexis

Hello Alexis,

No, everything is now connected (Sense + FETs).

Thanks,
Ronan

Hello Alexis_H, Luis H. S.,

Were the stack/pack/ld voltages calibrated on the TIDA-010247?

Thanks,
Ronan

Hi Ronan,

I am the designer of TIDA-010247. I didn't add the LD/PACK calibration code in the sample code. I was not required to achieve high accuracy for these voltage measurement. It seems you are on the right way to calibrate it. What's the difficulty now?

BRs

Kian

Hello Kian Lin,

OK nice to have direct contact with the designer of the TIDA!

The calibration is now OK for STACK voltage (even if gains/offsets for TOP/BOT BQs are quite different compared to the default value which seems a bit strange).

Still the calibration of LD/PACK voltages doesn't provide correct values compared to the input power supply.

I would say it is because Vdiv_offset is computed on STACK voltage but the Vdiv_offset should be different for LD/PACK on a TIDA like design.

From the calibration script:

Vdiv_Offset_cV = (
    TOS_Gain * (TOS_Voltage_Counts_A / N_SAMPLES) / 2 ** 16 - TOS_V1_cV
)

Vdiv_Offset = round(Vdiv_Offset_cV / (100.0 * vscale))  # Convert to UserV

Hi Ronan,

The back-calculated Vdiv offset should not be a big value, right? It seems you have 6~8V error when have 48V power supply. 

Did you try to calculate PACK and LD voltage via the Gain*raw count/2**16? 

BRs

Kian

Just focusing on BOTTOM BQ.

The STACK voltages are correct with the following offsets/gains after calibration:

BOTTOM

VDiv Offset                -640                
TOS Gain                   17131

At 30V power supply Stack is 15V for both BQs (OK calibration target value was 15V)
At 48V power supply Stack is 24V for both BQs (OK calibration target value was 24V)

The PACK/LD are incorrect with the following gains after calibration.

BOTTOM

Pack Gain                  32285               
LD Gain                     19500

At 30V power supply Pack is 24V and LD is 19.6V (KO calibration target value was 30V)
At 48V power supply Pack is 42V and LD is 37.8V (KO calibration target value was 48V)

=> So a ~6V error for PACK voltage and ~10V for LD Voltage.

> Did you try to calculate PACK and LD voltage via the Gain*raw count/2**16? 

It is what the calibration script is doing but will double check.

Ronan

Hi Ronan,

I see. I will try the calibration on my own board next week.

BRs

Kian

Hi Kian,

Thanks for the experiment.

So a gain of ~1.8 for PACK and ~1.6 for LD.

I will try a method that applies the gains for PACK/LD on the software side but it should work fine.

Is it ok for the internal securities / algorithms of the BQ if the PACK/LD are not calibrated? (especially the load detection).

Thanks,
Ronan